CDR Frequency Detector Using Additional Error Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock data recovery (CDR) systems have limited frequency acquisition range, leading to lock loss and communication link failure when the frequency difference between the transmitted signal and local clock exceeds the CDR's bandwidth, particularly in high-speed data communication systems.
Innovation Solution
Incorporating a frequency detector (FD) into the CDR circuitry that generates additional error signals to broaden the frequency acquisition range, allowing the detection of frequency offsets and enabling reliable clock recovery beyond the conventional CDR bandwidth limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional phase detector (PD) based CDR implementation is used, then the CDR can track instantaneous phase difference within its loop bandwidth, but the frequency acquisition range is limited to a small range (a few MHz, corresponding to a couple hundred ppm at 50+Gbps)
Solution Approach 1:
The invention segments the frequency detection function from the conventional phase detector by introducing a separate frequency detector (FD) that operates in parallel. The FD processes error signals through additional slicers to generate frequency offset information independently, while the PD continues to handle phase difference tracking. This segmentation allows each detector to be optimized for its specific function, enabling the system to acquire frequency over a wide range while maintaining precise phase tracking within the loop bandwidth.
Solution Approach 2:
The invention introduces additional error signals as intermediaries that carry frequency offset information from the slicers to the frequency detector. These error signals serve as mediators that bridge the gap between the conventional PD output and the frequency acquisition function, enabling the FD to detect frequency offsets beyond the limited bandwidth of the PD without interfering with the existing phase tracking mechanism.
2Adaptability or versatility
If the CDR bandwidth is increased to expand frequency capture range, then the frequency acquisition range improves, but the loop becomes unstable due to high loop latency
Solution Approach 1:
The invention segments the frequency tracking function into a separate frequency detector pathway that operates independently from the phase-locked loop. The FD processes error signals through additional slicers and generates frequency offset information that updates the phase interpolator directly, bypassing the bandwidth-limited PD pathway. This segmentation allows the system to achieve wide frequency capture range without increasing the CDR bandwidth, thereby maintaining loop stability despite high loop latency in ADC-based designs.
3Device complexity
If the CDR relies solely on phase difference information from the PD, then the implementation is simpler, but the frequency difference tracking capability is limited to small offsets (a few hundred ppm)
Solution Approach 1:
The invention segments the detection function into two parallel pathways: the conventional PD pathway for phase difference tracking and a new FD pathway for frequency offset tracking. The FD includes additional slicers that generate error signals specifically for frequency detection, and a frequency detector that processes these signals to produce frequency offset information. This segmentation enables the system to track large frequency offsets (beyond a few hundred ppm) while maintaining the simplicity of the original PD implementation for phase tracking.
Solution Approach 2:
The invention makes the error signal generation universal by using the same slicers to generate both phase error signals for the PD and frequency error signals for the FD. The additional error signals are derived from the same input data stream through the additional slicers, allowing both detectors to operate from a common error signal source. This multi-functionality approach enables frequency offset tracking beyond the PD's limited range without requiring completely separate error signal generation paths.
Data Source
AI summary
An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.