CDR Frequency Hold Using Stored Ratio for Fast Reacquisition

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Solution Overview

Problem

Conventional clock and data recovery (CDR) devices face challenges in rapidly reacquiring phase when the frequency of a communication signal is unknown or varies, leading to data loss during temporary interruptions or bursty transmissions, as they rely on predetermined frequencies and require lengthy frequency reacquisition processes.

Innovation Solution

A system and method that utilize a rotational frequency detector (RFD) and phase-frequency detector (PFD) to hold the frequency of a non-synchronous communication signal, allowing adaptation to small variations in data rate and maintaining a stable clock, even during signal loss, by using a calculated frequency ratio and a single reference frequency to generate a synthesized signal that matches the input signal frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional CDR devices use predetermined frequencies and XOR-based phase detectors, then the system is simple to implement, but the frequency reacquisition time is excessively long during signal interruptions

Engineering Contradiction:
Improvefrequency reacquisition timeVSAvoidsystem complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system performs preliminary frequency ratio detection and calculation during the locked state, storing the calculated ratio in a register before signal loss occurs. When signal interruption happens, the stored ratio is immediately retrieved and used to set the VCO frequency, eliminating the need for lengthy frequency sweeping during reacquisition.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A frequency ratio detector and calculator are introduced as intermediary components between the phase detector and VCO. These components calculate the ratio between VCO frequency and reference frequency, using this ratio to rapidly determine the new frequency setting during reacquisition, thereby reducing the overall system complexity compared to wide-bandwidth PLL approaches.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the VCO tuning range is widened to handle unknown frequencies, then the system becomes more adaptable to frequency variations, but the frequency discrimination capability of the phase detector becomes insufficient

Engineering Contradiction:
Improvefrequency range adaptabilityVSAvoidfrequency discrimination capability
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The frequency acquisition process is segmented into two distinct phases: a coarse frequency acquisition phase using the frequency ratio detector to bring the VCO close to the target frequency, and a fine tuning phase using the phase detector to achieve precise frequency and phase lock. This segmentation allows each component to operate within its optimal range.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically switches between different detection modes based on the acquisition state. During initial acquisition, the frequency ratio detector is active to handle large frequency offsets. Once near-lock is achieved, the system transitions to phase detector mode for precise frequency discrimination, adapting the measurement precision to the current operational requirements.

Inventive Principle:
Principle #15Dynamics

3Reliability

If auxiliary frequency acquisition systems are added to handle wide tuning ranges, then the system can acquire unknown frequencies, but data loss occurs during lengthy reacquisition processes

Engineering Contradiction:
Improveacquisition reliabilityVSAvoidreacquisition time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system continuously monitors the lock status through the phase detector and maintains the calculated frequency ratio in a register. Upon detecting loss of lock, the feedback mechanism immediately triggers retrieval of the stored ratio and rapid reconfiguration of the VCO frequency, minimizing reacquisition time and preventing data loss during transitions.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8094754B2Frequency hold mechanism in a clock and data recovery device
Publication Date: 2012.01.10 MACOM CONNECTIVITY SOLUTIONS LLC
  • US8094754B2 patent drawing
  • US8094754B2 patent drawing
  • US8094754B2 patent drawing

AI summary

A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency.