CDR Frequency Detector for Wide Frequency Offset Acquisition
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Solution Overview
Problem
Conventional clock data recovery (CDR) systems have limited frequency acquisition range, leading to lock loss and communication link failure when the frequency difference between the transmitted signal and local clock exceeds the CDR's bandwidth, particularly in high-speed data communication systems.
Innovation Solution
Incorporating a frequency detector (FD) into the CDR circuitry, which generates additional error signals to broaden the frequency acquisition range by processing data and error signals to produce a frequency vote, and multiplying this output by a user-defined gain to enhance the frequency path, allowing for more robust frequency detection beyond conventional CDR bandwidth limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase detector (PD) based CDR is used, then the CDR can track instantaneous phase difference within loop bandwidth, but the frequency acquisition range is limited to a small range (a few MHz, corresponding to a couple hundred ppm at 50+Gbps)
Solution Approach 1:
The invention segments the frequency detection function into two distinct components: a phase detector (PD) for tracking instantaneous phase differences within the loop bandwidth, and a frequency detector (FD) for detecting larger frequency offsets. This segmentation allows each detector to specialize in its respective range, with the PD maintaining precision for small phase differences and the FD extending the overall frequency acquisition range to several GHz, resolving the contradiction between tracking precision and frequency range adaptability.
2Adaptability or versatility
If CDR bandwidth is increased to expand frequency capture range, then the frequency acquisition range improves, but the loop becomes unstable due to high loop latency
Solution Approach 1:
The frequency detector (FD) acts as an intermediary component that bridges the gap between the phase detector and the phase interpolator. The FD detects larger frequency offsets and generates frequency votes that are integrated into the control signal, enabling the CDR to acquire and track frequencies beyond the conventional bandwidth limit without requiring an increase in loop bandwidth that would cause instability. This intermediary function allows the loop to maintain stability while expanding the frequency capture range to several GHz.
3Speed
If ADC based designs are used, then the CDR can process high-speed data, but the loop latency limits the CDR bandwidth and frequency capture range
Solution Approach 1:
The invention replaces the conventional ADC-based frequency detection mechanism with a direct voltage-based frequency detector that operates in the analog domain. Instead of converting signals to digital for processing (which introduces loop latency), the FD directly processes analog voltage signals to generate frequency votes. This substitution eliminates the digital conversion bottleneck, maintaining high-speed data processing capability while reducing loop latency and enabling broader frequency capture range without compromising speed.
Data Source
AI summary
An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.