CDR Frequency Detection Circuit for Large Clock Offset Tracking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock data recovery (CDR) circuits face difficulties in tracking frequency differences between data and clock signals, leading to limited adjustment capabilities and potential system instability, especially when frequency differences are large.
Innovation Solution
A single-loop frequency detection circuit incorporating a phase detector, delayers, and a logic circuit that samples data signals according to clock signals with specific delays to generate a clock instruction signal for adjusting the clock frequency, allowing for more effective tracking of both phase and frequency differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional single-loop CDR circuit is used, then the circuit structure is simple, but it cannot track large frequency differences between data and clock signals
Solution Approach 1:
The patent divides the frequency detection function into multiple detection stages by using different delay values (first delay, second delay, third delay) to create multiple sampling points. This segmentation allows the circuit to detect frequency differences of various magnitudes, enabling tracking of large frequency deviations while maintaining a single-loop structure.
Solution Approach 2:
The patent introduces a temporal dimension by using multiple delay stages to sample the data signal at different time points relative to the clock signal. This transforms the frequency detection from a single-point measurement to a multi-point temporal analysis, enabling the detection of large frequency differences through the pattern of sampling results across different delays.
2Adaptability or versatility
If a dual-loop CDR circuit is used, then large frequency differences can be tracked, but the complexity of determining adjustment differences between charge pumps increases
Solution Approach 1:
The patent merges the phase detection and frequency detection functions into a single integrated detector. The same detection circuit uses different delay configurations to perform both phase error detection and frequency error detection, eliminating the need for separate dual-loop structures and simplifying the determination of adjustment differences.
Solution Approach 2:
The detection circuit is designed with multi-functionality, serving both as a phase detector and a frequency detector. By using the same detection mechanism with variable delay settings, the circuit can handle both phase alignment and frequency tracking tasks, reducing the complexity associated with dual-loop architectures.
3Measurement precision
If conventional phase detection is used, then phase tracking is achieved, but frequency tracking capability is limited
Solution Approach 1:
The patent introduces dynamic delay adjustment to the detection circuit. The delay values are not fixed but can be adjusted based on the detected frequency difference, allowing the circuit to adapt its sampling points dynamically. This dynamic capability enables the circuit to maintain accurate phase detection while simultaneously acquiring frequency information through appropriate delay selection.
Solution Approach 2:
The delay elements serve as intermediaries between the clock signal and the detection process. By introducing controlled delays, the circuit can sample the data signal at multiple phases relative to the clock, using these delayed samples as intermediary measurements to infer both phase and frequency information without requiring separate detection mechanisms.
Data Source
AI summary
A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal.