CDR Circuit with Frequency-Phase Switching for Scalable Power
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Solution Overview
Problem
Conventional clock and data recovery (CDR) circuits face challenges with high power consumption and unscaled power loss, particularly at varying data rates, due to limited tuning range and increased phase noise in voltage-controlled oscillators, and are not suitable for low supply voltages.
Innovation Solution
A circuit arrangement with a frequency regulation circuit and a phase regulation circuit, utilizing a state machine, current digital/analog converter, current/voltage converter, and voltage-controlled oscillator, where resistive loads are replaced by NMOS transistors to vary conductive values and output loads based on oscillator frequency, enabling scalable power loss with data rate and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a voltage-controlled LC oscillator is used to achieve low phase noise, then phase noise is reduced, but the tuning range becomes small and chip surface area increases
Solution Approach 1:
The patent uses a voltage-controlled ring oscillator where the oscillation frequency can be dynamically adjusted over a wide range (factor of 5 or more) by controlling the voltage at pins VBNF and VBNS. This dynamic control enables the oscillator to adapt to different data rates while maintaining low phase noise through the CML implementation.
Solution Approach 2:
The patent replaces the mechanical LC resonator with an electronic ring oscillator implementation using CML logic stages. This substitution eliminates the need for large on-chip inductors while achieving comparable or better phase noise performance with a much smaller footprint and wider tuning range.
2Adaptability or versatility
If a voltage-controlled ring oscillator is used to achieve wide tuning range, then tuning range is increased, but output jitter increases due to higher phase noise
Solution Approach 1:
The patent implements the ring oscillator using CML (Current Mode Logic) technology, which provides superior phase noise characteristics compared to conventional voltage-mode ring oscillators. The CML implementation maintains signal integrity and reduces jitter even across wide tuning ranges.
Solution Approach 2:
The patent changes the operating parameters of the ring oscillator by controlling the voltage at specific pins (VBNF, VBNS) to adjust the oscillation frequency. This voltage control mechanism enables wide tuning range while the CML architecture maintains low phase noise through consistent current operation.
3Adaptability or versatility
If an additional divider circuit is added to achieve higher frequency variation, then frequency tuning range is increased, but power consumption increases
Solution Approach 1:
The voltage-controlled ring oscillator is designed to provide both frequency division and frequency multiplication capabilities through its wide intrinsic tuning range. This eliminates the need for separate divider circuits, as the oscillator itself can operate at different effective frequencies to achieve the same functional result with lower power consumption.
Solution Approach 2:
The oscillator uses dynamic voltage control at pins VBNF and VBNS to achieve frequency variation up to a factor of 5 or more without requiring additional static power-consuming divider circuits. The dynamic adjustment allows the same hardware to cover a wide frequency range efficiently.
4Stability of the object's composition
If conventional CDR circuits are used to maintain fixed power loss, then power stability is maintained, but scalability with data rate is lost
Solution Approach 1:
The patent implements a CDR circuit where power consumption dynamically scales with the data rate through the voltage-controlled ring oscillator. As the data rate increases, the oscillator frequency increases, and power consumption adjusts accordingly. This dynamic behavior enables efficient operation across different data rates without wasting power at lower rates.
Solution Approach 2:
The circuit changes its operating parameters (voltage at control pins, oscillation frequency) based on the required data rate. This parameter adjustment allows the power loss to scale proportionally with the data rate, optimizing energy efficiency while maintaining stable operation at each operating point.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a large tuning range with low power loss, reducing power consumption and allowing operation at low supply voltages, with power loss scaling with data rate, and optimizing conductive and output loads for efficient clock and data recovery.
Implementation Method 1
the frequency of the ring oscillator can be altered via a variation of the voltage at the pins VBNF and VBNS
Implementation Method 2
the necessary logic blocks of the phase detector are normally implemented in C[urrent]M[ode]L[ogic]
Data Source
AI summary
In order to provide a circuit arrangement (100) and also a method for clock and/or data recovery (CDR) having low power consumption, having low power loss and also having scalability of the power loss from the clock and/or data recovery at the data rate,at least one frequency regulation circuit andat least one phase regulation circuitare proposed, wherein firstly only the frequency regulation circuit is active for the purpose of setting the frequency on the basis of the data rate that can be applied to the data input and then changeover to the phase regulation circuit occurs for the purpose of ascertaining the phase difference between the data input and the clock input.