CDR Frequency Correction for Low-Accuracy Resonator Clocks
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Solution Overview
Problem
Existing semiconductor devices require a long time to detect frequency errors in high-speed serial communication, limiting the generation of highly accurate clock signals necessary for increased communication speeds.
Innovation Solution
A semiconductor device with a clock-and-data recovery circuit that includes a phase tracking loop and a frequency tracking loop, along with a frequency error adjuster, allows for rapid frequency correction of the transmission clock by comparing the phase and frequency of the synchronization clock with the input signal, using a digital CDR and PLL circuit to generate a highly accurate clock from a low-accuracy resonator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a resonator with lower accuracy than quartz resonator is used to generate the transmission clock, then system cost is reduced, but the accuracy of the clock signal deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the receiver detects frequency errors in the received signal and transmits correction information back to the transmitter. The transmitter uses this feedback to adjust its transmission clock frequency, thereby compensating for the lower accuracy of the resonator and achieving high clock signal accuracy without using expensive quartz resonators
Solution Approach 2:
The patent replaces the mechanical/quartz resonator-based clock generation system with a digitally controlled system. The transmission clock is generated by a voltage-controlled oscillator (VCO) whose frequency is adjusted based on digital correction information from the receiver, substituting the purely mechanical quartz resonator system with an electronically controllable system
2Device complexity
If analog processing is used to calculate phase difference between reception signal and transmission signal, then device complexity is reduced, but the time required to detect frequency error increases
Solution Approach 1:
The patent replaces analog phase difference calculation with digital signal processing. The receiver uses digital correlation processing to detect frequency errors, which significantly reduces the detection time compared to analog methods while maintaining reasonable system complexity through software or digital logic implementation
Data Source
AI summary
A semiconductor device includes a clock-and-data recovery circuit including a phase tracking loop that generates a phase difference signal indicating a phase difference between a reception clock generated from a transmission clock and an input signal and makes the reception clock track the input signal, a frequency tracking loop that performs control to make a frequency of the reception clock track a frequency of the input signal, the clock-and-data recovery circuit being configured to extract a data signal and a synchronization clock from the input signal and to control a phase and a frequency of the reception clock, a frequency error adjuster that increases or decreases a value indicated by a frequency adjustment signal according to a frequency difference signal generated based on the phase difference signal, and an oscillator that increases or decreases a frequency of the transmission clock based on the frequency adjustment signal.