CDR Circuitry Frequency Scaling for Multi-Protocol Speed Negotiation

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Solution Overview

Problem

Existing clock and data recovery (CDR) circuitry in integrated circuits lacks the ability to support a wide range of high-speed serial data communication protocols and frequencies, particularly in general-purpose devices like programmable logic devices and field-programmable gate arrays, which limits their adaptability and efficiency in various applications.

Innovation Solution

The integration of CDR circuitry with frequency and phase scaling capabilities, including a phase-locked loop with charge pump circuitry and voltage-controlled oscillator, along with controllable charge pump current and voltage regulator, allows for adaptable operation across multiple protocols and frequencies, enabling auto-speed negotiation and supporting protocols like PCIE Gen1, Gen2, and Gen3, as well as Quick Path Interconnect.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If CDR circuitry is designed for a specific frequency range to ensure stable operation, then reliability is improved, but adaptability to different communication protocols deteriorates

Engineering Contradiction:

Improvestable clock and data recoveryVSAvoidsupport for multiple protocols

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamically adjustable frequency scaling circuitry that can modify the frequency of reference clock signals and data signals in real-time. This allows the CDR circuitry to adapt its operating frequency range while maintaining stable lock, enabling support for multiple communication protocols (PCIE Gen1/Gen2/Gen3, QPI) without sacrificing reliability

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes key operating parameters including frequency scaling factors, charge pump current levels, and voltage regulator outputs to optimize performance across different protocols. By dynamically adjusting these parameters, the circuit maintains stable operation while adapting to different data rates from 622 Mbps to 12.5 Gbps

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If frequency scaling circuitry is added to support multiple protocols, then adaptability is improved, but device complexity increases

Engineering Contradiction:

Improvemulti-protocol supportVSAvoidcircuit structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent designs universal frequency scaling circuitry that serves multiple functions: it scales reference clock signals for different protocols, scales recovered data signals, and provides auto-speed negotiation capability. This multi-functional approach enables broad protocol support while minimizing the addition of separate dedicated circuits for each function

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines frequency scaling, phase adjustment, and protocol detection functions into integrated circuit blocks. The frequency scaling circuitry is merged with the phase-locked loop and charge pump circuitry, creating a unified system that reduces overall device complexity compared to having separate independent circuits for each function

Inventive Principle:

Principle #5Merging (Combining)

3Ease of operation

If auto-speed negotiation is implemented, then ease of operation is improved, but loss of time during speed switching increases

Engineering Contradiction:

Improveautomatic speed switchingVSAvoidspeed transition delay

Core Design Contradiction:

Ease of operationVSLoss of time

Solution Approach 1:

The patent implements preliminary frequency scaling preparation where the frequency scaling circuitry pre-configures appropriate scaling factors based on detected protocol requirements. This preliminary action allows the system to switch between speeds more quickly by having scaling parameters ready in advance, reducing the time loss during speed transitions

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables continuous multi-rate operation from 622 Mbps to 12.5 Gbps, supports auto-negotiation between different speed standards, and provides stable clock and data recovery with low jitter, enhancing the adaptability and efficiency of CDR circuitry in various high-speed serial data communication scenarios.

Implementation Method 1

voltage-controlled oscillator circuitry coupled to one another in a closed loop series

Methodology Applied

Scientific EffectVoltage-controlled oscillation:

Implementation Method 2

charge pump circuitry, voltage-controlled oscillator circuitry, and phase-frequency detector circuitry coupled to one another in a closed loop series

Methodology Applied

Scientific EffectCharge pump:

Data Source

PatentUS8811555B2Clock and data recovery circuitry with auto-speed negotiation and other possible features

Publication Date: 2014.08.19 ALTERA CORP

AI summary

An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).