CDR Circuit Frequency Scaling for Auto-Negotiated Serial Data Rates
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Solution Overview
Problem
Current clock and data recovery (CDR) circuitry in integrated circuits lacks the ability to dynamically adjust to various high-speed serial data communication protocols and frequencies, limiting its versatility and adaptability in supporting multiple standards like PCIE Gen1, Gen2, and Gen3, and other protocols such as Quick Path Interconnect (QPI), without the need for reprogramming or resetting.
Innovation Solution
The CDR circuitry includes controllable frequency scaling elements and separate control circuitry that monitor data changes to adjust its operation, supporting auto-speed negotiation and a wide range of data rates by using phase-locked loop (PLL) circuitry with charge pump and voltage-controlled oscillator (VCO) components, along with variable voltage regulators, to dynamically adjust to different communication protocols and frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CDR circuitry is designed for a fixed frequency and protocol, then it achieves stable and reliable operation, but it lacks adaptability to support multiple communication standards and data rates
Solution Approach 1:
The patent implements dynamic frequency scaling capability in the CDR circuitry, allowing it to adapt to different data rates (2.5 Gbps, 5.0 Gbps, 8.0 Gbps) by dynamically adjusting the frequency multiplication factor. The frequency scaler can be controlled to operate at different scaling ratios, enabling the same hardware circuit to support multiple PCIE generations without requiring separate dedicated circuits for each protocol.
Solution Approach 2:
The CDR circuitry is designed with universal functionality to support multiple communication protocols and standards through a single integrated circuit. By incorporating controllable frequency scaling elements and auto-speed negotiation capability, the circuit can function across different PCIE generations (Gen1, Gen2, Gen3) and potentially other high-speed serial protocols, eliminating the need for multiple specialized circuits.
2Adaptability or versatility
If CDR circuitry supports multiple data rates through frequency scaling, then adaptability improves, but circuit complexity and control requirements increase
Solution Approach 1:
The patent implements auto-speed negotiation capability that allows the CDR circuitry to automatically detect and adapt to the required data rate without external intervention. The circuit autonomously monitors the communication protocol requirements and adjusts its frequency scaling factor accordingly, eliminating the need for complex external control logic and simplifying the overall system architecture.
Solution Approach 2:
The control circuitry monitors the recovered data stream to detect communication change requests and automatically adjusts the frequency scaling factor based on feedback from the data rate detection. This closed-loop control mechanism enables the circuit to self-regulate and adapt to different protocols dynamically, reducing the complexity of manual configuration and control.
3Adaptability or versatility
If frequency scaling is implemented to support variable data rates, then operational flexibility increases, but stability and precision of clock recovery may be compromised
Solution Approach 1:
The patent employs a phase-locked loop (PLL) with dynamic frequency scaling capability that maintains phase coherence while adapting to different data rates. The PLL architecture ensures that even when the frequency multiplication factor changes, the recovered clock remains phase-aligned with the incoming data stream, preserving timing precision and signal integrity across all operating conditions.
Solution Approach 2:
The circuit implements controlled parameter changes in the frequency scaling factor while maintaining other critical parameters within acceptable ranges. By carefully managing the frequency multiplication ratio and adjusting associated loop filter parameters in the PLL, the system achieves variable data rate support while preserving clock recovery stability and meeting jitter specifications for each operating mode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables continuous multi-rate operation from 622 Mbps to 12.5 Gbps, supports PCIE Gen2 and Gen3 auto-negotiation, and various other protocols, ensuring stable clock and data recovery without reprogramming, thus enhancing the adaptability and efficiency of the CDR circuitry in integrated circuits.
Implementation Method 1
voltage-controlled oscillator (VCO) components, along with variable voltage regulators, to dynamically adjust to different communication protocols and frequencies
Implementation Method 2
phase-locked loop (PLL) circuitry with charge pump and voltage-controlled oscillator (VCO) components
Data Source
AI summary
An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.