CDR Circuit with Internal Jitter Injection for Tolerance Testing

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Solution Overview

Problem

Conventional clock and data recovery circuits require expensive external instruments for jitter tolerance testing, leading to increased circuit size and inaccurate estimation of jitter amplitude due to the use of analog circuits.

Innovation Solution

A clock and data recovery circuit with a built-in jitter tolerance test, incorporating a sampler, phase detector, filter, and phase digital-to-analog converter, which imposes jitter internally to test tolerance, reducing circuit size and enabling accurate jitter amplitude estimation through digital circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional circuits are used to impose jitter on a data stream, then jitter tolerance testing can be performed, but the circuit size increases

Engineering Contradiction:

Improvejitter tolerance testing capabilityVSAvoidcircuit size

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the jitter source functionality with the existing CDR circuit by utilizing the phase detector and digital-to-analog converter that are already present in the CDR structure. The jitter is imposed through the existing control path without adding separate external jitter injection circuits, thereby enabling jitter tolerance testing while avoiding increases in circuit size.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The phase detector and digital-to-analog converter in the CDR circuit serve dual purposes: they function as normal phase detection and clock recovery components, and simultaneously serve as jitter injection mechanisms when needed for testing. This multi-functionality eliminates the need for dedicated jitter generation circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If analog circuits are used to impose jitter, then jitter can be generated, but the jitter amplitude cannot be estimated accurately due to variations with voltages, temperatures and manufacturing processes

Engineering Contradiction:

Improvejitter generation capabilityVSAvoidjitter amplitude estimation accuracy

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The patent replaces analog jitter generation circuits with a digital implementation. The jitter source generates digital control words that are processed through the existing digital filter and digital-to-analog converter. This digital approach eliminates the sensitivity to voltage, temperature, and manufacturing process variations that plagues analog circuits, enabling accurate estimation and control of jitter amplitude.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the implementation approach from analog to digital domain. By generating jitter through digital control words and using a digital filter, the system gains precise control over jitter parameters. The digital implementation allows for accurate estimation of jitter amplitude since digital circuits do not exhibit the same sensitivity to environmental variations as analog circuits.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8953668B2Method and circuit of clock and data recovery with built in jitter tolerance test

Publication Date: 2015.02.10 REALTEK SEMICON CORP

AI summary

A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.