Clock Data Recovery Jitter Bandwidth Trade-off
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Solution Overview
Problem
Current clock and data recovery (CDR) systems face challenges in achieving a balance between high bandwidth for tracking frequency jitters and low jitter to prevent excessive phase movement, which is crucial for maintaining accurate data recovery in high-speed digital circuits.
Innovation Solution
A method involving the acquisition of early, optimal, and late votes, determining and weighting allowed votes, disallowing votes that would move the CDR to extreme zero crossings, and adjusting the recovered clock phase based on accumulated votes to minimize jitter and maximize bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the CDR bandwidth is increased to track higher frequency jitters, then the ability to filter noise and deterministic jitter is improved, but the CDR jitter increases causing excessive phase movement
Solution Approach 1:
The patent implements dynamic bandwidth control by adjusting the CDR loop bandwidth based on operating conditions. The system transitions between different bandwidth modes (e.g., high bandwidth for noise filtering, low bandwidth for jitter reduction) depending on the signal quality and jitter characteristics, allowing the CDR to adaptively optimize both noise rejection and jitter performance
Solution Approach 2:
The patent changes the CDR loop bandwidth parameter dynamically to resolve the contradiction. By adjusting this key parameter based on detected signal conditions, the system can achieve high bandwidth when needed for noise filtering while maintaining low jitter when required for stable phase tracking
2Reliability
If the CDR bandwidth is decreased to reduce CDR jitter, then the phase stability is improved, but the ability to track higher frequency jitters is reduced
Solution Approach 1:
The system dynamically adjusts the CDR bandwidth based on real-time signal conditions. When the signal exhibits high jitter content, the bandwidth is reduced to improve phase stability. When the signal quality is good and noise filtering is needed, the bandwidth is increased to enhance tracking capability
3Speed
If a PLL-based CDR method is used to achieve high bandwidth, then the tracking capability is improved, but the area and power consumption increase
Solution Approach 1:
The patent employs a simplified CDR architecture that avoids complex PLL circuits. Instead, it uses a more economical approach with reduced hardware complexity that achieves adequate tracking capability while significantly lowering power consumption and area requirements, suitable for cost-sensitive applications
4Speed
If a PLL-based CDR method is used to achieve high bandwidth, then the tracking capability is improved, but the area increases
Solution Approach 1:
The patent uses a simplified CDR implementation that replaces area-intensive PLL components with more compact circuitry. The design achieves acceptable tracking performance with significantly reduced area footprint, making it suitable for integrated circuits with area constraints
Data Source
AI summary
A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase.