Clock Data Recovery Circuit Jitter Tolerance Testing
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Solution Overview
Problem
Existing testing methods for clock data recovery circuits face challenges in isolating the performance of these circuits due to data-dependent clock jitter, making it difficult to diagnose whether poor performance is caused by the clock data recovery circuit or the receiver front-end circuit, and are often costly due to the use of error detectors with pseudorandom binary sequences of multiple frequencies.
Innovation Solution
A testing system and method utilizing a signal generator to produce a clock pattern signal with a single frequency, combined with a jitter signal, allowing direct assessment of the clock data recovery circuit's performance by an oscilloscope, excluding the influence of other circuits and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pseudorandom binary sequences of multiple frequencies are used for testing, then comprehensive performance evaluation is achieved, but cost increases due to expensive error detectors
Solution Approach 1:
The patent extracts and isolates the clock data recovery circuit performance from the overall system performance by using a single-frequency clock pattern signal. This allows direct measurement of the CDR circuit's jitter tolerance without the need for expensive error detectors, as the single frequency eliminates data-dependent jitter interference that would otherwise require complex multi-frequency pseudorandom sequences for accurate evaluation
Solution Approach 2:
The patent changes the testing parameter from multi-frequency pseudorandom binary sequences to a single-frequency clock pattern signal. This parameter change simplifies the testing methodology while maintaining measurement precision for CDR circuit performance, specifically for evaluating jitter tolerance without requiring costly error detection equipment
2Reliability
If multi-frequency pseudorandom binary sequences are used, then complete system performance is tested, but it becomes difficult to isolate clock data recovery circuit performance
Solution Approach 1:
The patent segments the testing approach by using a single-frequency clock pattern signal instead of multi-frequency pseudorandom sequences. This segmentation isolates the clock data recovery circuit's specific performance characteristics, allowing clear diagnosis of CDR circuit jitter tolerance without the confounding effects of data-dependent jitter from multiple frequencies
Solution Approach 2:
The single-frequency clock pattern signal acts as an intermediary that mediates between the test stimulus and the clock data recovery circuit. This intermediary eliminates data-dependent jitter interference, providing a clean measurement signal that directly reveals CDR circuit performance without requiring complex multi-frequency analysis
Data Source
AI summary
A testing system includes a signal generator circuit, a jitter modulation circuit, and an oscilloscope circuit. The signal generator circuit is configured to generate a clock pattern signal with a single clock pattern frequency. The jitter modulation circuit is configured to generate a jitter signal. A device-under-test is configured to receive an input signal. The input signal is a combination signal of the clock pattern signal and the jitter signal. The device-under-test includes a clock data recovery circuit and is further configured to generate an output signal according to the input signal. The oscilloscope circuit is configured to receive the output signal for determining performance of the clock data recovery circuit.