CDR Lock Detection Circuit for Imbalanced Early-Late Vote Ratios
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Solution Overview
Problem
High-speed communications systems face challenges in maintaining accurate clock recovery due to imbalances in early and late vote ratios, leading to potential false lock detections and inefficient data communication rates, especially at higher data rates where DFE compensation calculations are incomplete in time.
Innovation Solution
The method generates early and late votes for a clock recovery system, calculating first and second early-late vote measurements reflective of imbalances during different time intervals, and outputs a CDR-lock signal if these ratios are within a predetermined threshold, ensuring accurate clock locking and minimizing false lock reports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If receive sampling is performed at twice the expected data reception rate (double-baud-rate), then independent detection of data component and clock component is improved, but receiver power utilization increases substantially
Solution Approach 1:
The patent segments the sampling process by using two distinct time samples per receive unit interval to separately detect data component and clock component, enabling independent detection while operating at baud rate instead of double-baud-rate, thus reducing power consumption while maintaining measurement precision
Solution Approach 2:
The patent dynamically adjusts the sampling strategy by using speculative DFE computations that adapt to whether the determining data bit resolves to one or zero, allowing the system to maintain accurate detection at baud rate by making intelligent predictions about future states based on current conditions
2Productivity
If DFE compensation calculations are performed at higher data rates, then data communication rate is improved, but calculation completion time decreases causing incomplete compensation
Solution Approach 1:
The patent performs preliminary DFE compensation calculations on speculative or potential data values before the actual data bit is resolved, using unrolled DFE stages that predict compensation values for both possible outcomes (one or zero), allowing the system to have compensation ready in advance without waiting for calculation completion
Solution Approach 2:
The patent implements dynamic speculative computation where the system maintains multiple potential compensation values simultaneously and selects the correct one based on the resolved data bit, enabling high-speed operation by eliminating the sequential dependency between detection and computation
3Speed
If early-late vote ratio comparison is performed without normalization, then lock detection speed is improved, but false lock detections increase
Solution Approach 1:
The patent changes the parameter being compared from raw early-late vote counts to normalized ratios, dividing the absolute difference by the sum of early and late votes to account for variations in total vote quantity, thereby maintaining detection speed while significantly improving reliability by reducing false lock detections
Solution Approach 2:
The patent replaces the simple mechanical counting comparison with a normalized ratio calculation that incorporates mathematical normalization, substituting the crude mechanical approach with a more sophisticated computational method that maintains speed through efficient arithmetic while improving accuracy
Data Source
AI summary
Methods and systems are described for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote measurements, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.