CDR Locking Phase Selection for High-Speed ISI Channels
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Solution Overview
Problem
Current systems for high-speed data communication face challenges in determining the optimal Clock and Data Recovery (CDR) locking phase, which affects the Bit Error Rate (BER) and overall performance due to Inter-Symbol Interference (ISI) and suboptimal interactions between CDR and Decision-Feedback Equalizer (DFE) loops.
Innovation Solution
A method and system that calculate the overall pulse response of the data communication system, determine the phase with a minimum function value, and set the CDR locking phase as this phase plus a midpoint, using a processor and components like a CDR phase detector, CTLE, DFE, and deserializer, to decouple the CDR from the DFE adaptation loop and reduce ISI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If advanced equalization schemes are used to reduce ISI, then communication reliability is improved, but system complexity increases due to optimal operation challenges
Solution Approach 1:
The patent changes the parameter of CDR locking phase from an unknown variable to a deterministically calculated value based on overall pulse response. By calculating the phase that minimizes the absolute value of the overall pulse response at the symbol decision point, the system optimizes equalization performance without requiring complex adaptive algorithms, thus improving reliability while controlling complexity.
Solution Approach 2:
The patent replaces complex adaptive equalization mechanisms with a analytical calculation approach. Instead of using complex adaptive algorithms to determine optimal CDR phase, the system uses direct mathematical calculation of the overall pulse response and its minimum point, substituting mechanical/adaptive systems with analytical methods.
2Reliability
If CDR and DFE loops are coupled for optimal operation, then equalization performance is improved, but system stability deteriorates due to interaction between loops
Solution Approach 1:
The patent extracts the CDR phase determination from the DFE adaptation loop by calculating it independently based on overall pulse response. The CDR locking phase is determined analytically before being applied to the DFE, separating the phase detection function from the equalization adaptation process, thus maintaining stability while preserving performance.
Solution Approach 2:
The patent performs preliminary calculation of the CDR locking phase using overall pulse response analysis before the DFE adaptation begins. By pre-determining the optimal phase that minimizes pulse response magnitude, the system establishes a stable foundation for subsequent equalization operations without loop interactions.
3Productivity
If high data rates are used to meet demand, then productivity is improved, but ISI increases due to dispersive channels
Solution Approach 1:
The patent changes the timing parameter of symbol decision by calculating the optimal CDR locking phase that minimizes overall pulse response at the decision point. This phase adjustment compensates for dispersive channel effects that cause ISI at high data rates, allowing maintained productivity while reducing interference through precise timing optimization.
Data Source
AI summary
A data communication system includes a transmitter, a channel, and a receiver includes a Clock and Data Recovery (CDR) phase detector that is configured to: calculate an overall pulse response of the data communication system; obtain a function value for each of a plurality of phases, the plurality of phases corresponding to a resolution per symbol; set a crossing phase to be a phase at which this value is minimum among the plurality of phase; and set the CDR locking phase to be the crossing phase plus a midpoint from among the plurality of phases.