CDR Logic Branching and Charge Pump for Low-Latency Speculative DFE
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Solution Overview
Problem
High-speed communications systems face challenges in achieving low latency and high data communication rates due to extraneous protocol transitions and the inability to calculate Decision Feedback Equalization (DFE) compensation in time at higher data rates, leading to increased receiver power utilization and complexity.
Innovation Solution
A multi-phase speculative DFE system that generates speculative DFE compensation values for potential data decisions, allowing for timely clock recovery and reduced latency by using a set of logic branches to select and generate output currents for a local oscillator controller, which adjusts the input voltage of a proportional control circuit through a charge pump circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If receive sampling is performed at twice the expected data reception rate to enable independent detection of data component and clock component, then clock data recovery capability is improved, but receiver power utilization increases substantially
Solution Approach 1:
The patent segments the received signal processing into separate data detection and clock recovery paths. The data sampler detects data at the expected data rate while a separate clock sampler detects clock transitions, allowing independent optimization of each function and avoiding the power penalty of double-rate sampling for both purposes.
Solution Approach 2:
The patent uses the same received signal for both data detection and clock recovery simultaneously. By processing the single received signal stream through multiple detection mechanisms operating at different rates, the system achieves multi-functionality without requiring separate high-rate sampling paths for each function.
2Measurement precision
If DFE compensation is calculated using historical data values at higher data rates, then equalization accuracy is improved, but computation completion time becomes insufficient for next data sample
Solution Approach 1:
The patent performs DFE compensation calculations using speculative data values in advance of when the actual data is known. By pre-calculating compensation for multiple possible data scenarios and storing these results, the system has equalization values ready when needed, eliminating computation delays during critical sampling intervals.
Solution Approach 2:
The patent dynamically selects among multiple pre-calculated DFE compensation values based on the actual resolved data bits. The system adapts its equalization approach in real-time by choosing the appropriate pre-computed compensation value that matches the actual data sequence, maintaining high equalization accuracy without real-time computation overhead.
3Loss of time
If unrolled DFE computations are performed on speculative data values rather than known previous data values, then computation time is reduced, but detection complexity increases
Solution Approach 1:
The patent pre-calculates DFE compensation for multiple speculative data scenarios and stores these results in lookup tables or memory structures. This preliminary computation eliminates the need for complex real-time calculations during the critical data sampling window, reducing detection complexity at the moment of decision while maintaining computational accuracy.
4Reliability
If extraneous communications protocol transitions are introduced to facilitate clock recovery, then clock signal extraction is improved, but achievable data communication rate is limited
Solution Approach 1:
The patent extracts clock information directly from the data signal transitions themselves rather than relying on extraneous protocol transitions. By detecting clock edges embedded in the actual data transitions, the system achieves clock recovery without adding artificial signaling overhead that would limit data communication rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient clock data recovery with reduced latency and increased PLL loop bandwidth, improving data communication rates while minimizing receiver power and complexity.
Implementation Method 1
the output current sourcing and sinking current to a capacitor through a resistive element to adjust the input voltage of the proportional control circuit
Implementation Method 2
sourcing and sinking current to a capacitor through a resistive element to adjust the input voltage
Data Source
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AI summary
Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.