CDR Loop Partitioning for Low-Power Clock Recovery
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Solution Overview
Problem
High-frequency clock and data recovery (CDR) systems in high-speed serial interfaces consume excessive power due to increased clock frequencies, which is not effectively addressed by existing technologies.
Innovation Solution
A CDR system with an integral-proportional control loop that executes the proportional path at a higher clock frequency and the integral path at a lower clock frequency, utilizing separate deserializers to process data streams with varying word lengths, allowing the integral path to operate at a significantly lower frequency to reduce power consumption while maintaining low latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the CDR system executes both proportional and integral paths at high clock frequency to maintain low latency, then tracking speed is improved, but power consumption increases
Solution Approach 1:
The control loop is segmented into two separate paths: a proportional path that executes at high clock frequency to provide fast phase tracking and low latency, and an integral path that executes at lower frequency to reduce power consumption while handling frequency adjustments. This segmentation allows each path to operate at optimally different frequencies based on their specific functional requirements.
Solution Approach 2:
The system dynamically adjusts the operating frequency of different control paths based on their specific needs. The proportional path maintains high frequency for rapid response to phase changes, while the integral path operates at lower frequency since frequency adjustments occur more slowly. This dynamic frequency allocation optimizes the balance between tracking performance and power consumption.
2Use of energy by moving object
If the integral path executes at lower clock frequency to reduce power consumption, then energy efficiency is improved, but latency may increase
Solution Approach 1:
By separating the control functions into distinct proportional and integral paths with different execution frequencies, the system ensures that time-critical phase tracking operations occur at high frequency while less time-sensitive frequency adjustments occur at lower frequency, minimizing overall latency impact.
Solution Approach 2:
The system uses feedback mechanisms where the proportional path continuously monitors phase errors and provides rapid corrections, while the integral path accumulates frequency error information and makes gradual adjustments. This feedback structure ensures that even though the integral path runs at lower frequency, the overall system maintains low latency through the high-frequency proportional path's continuous phase correction.
Data Source
AI summary
Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The proportional path may be executed at a first clock frequency, while the integral path may be executed at a second clock frequency that is lower than the first clock frequency to reduce the power consumption of the CDR system.