CDR Circuit Metastability Detection for Faster Clock Lock
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Solution Overview
Problem
Conventional clock-data recovery (CDR) circuits, particularly in high-speed serial signaling modes, face performance issues due to metastable states that prolong locking time, especially in burst modes, as they struggle to align data clocks with asymmetric data eyes and precursor inter-symbol interference.
Innovation Solution
The implementation of a CDR circuit with a bang-bang phase detector and a baud-rate phase detector, along with a control circuit that includes a metastable detector and phase adjust circuit, to quickly identify and resolve metastable states by dithering detection and phase adjustment, utilizing a multiplexer to select the appropriate phase-detect output based on operational modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional CDR circuit uses median-based sampling phase alignment, then the data clock can be aligned to the middle region of the data eye, but the locking time is prolonged due to metastable states
Solution Approach 1:
The circuit performs preliminary detection of metastable states using the metastable detector before final sampling phase alignment is completed. By detecting metastable conditions early in the locking process, the circuit can trigger corrective phase adjustments before the metastability prevents proper locking, thereby reducing overall locking time while maintaining alignment accuracy
Solution Approach 2:
The metastable detector provides feedback about metastable states to the phase adjust circuit, which then modifies the sampling phase accordingly. This feedback mechanism allows the circuit to dynamically correct metastability issues during the locking process, resolving the contradiction between maintaining accurate median-based alignment and reducing locking time
2Speed
If a bang-bang CDR circuit is used to achieve fast locking, then locking speed improves, but metastable states arise that prolong the actual lock time
Solution Approach 1:
The metastable detector acts as an intermediary between the bang-bang phase detector and the phase adjust circuit. It monitors the output of the bang-bang detector and identifies when metastable states are present, then triggers appropriate corrective actions. This intermediary component allows the circuit to maintain the fast response of bang-bang detection while adding stability by detecting and correcting metastability issues
3Ease of operation
If the sampling phase is positioned at one-half bit period, then ideal symmetric sampling is achieved, but asymmetric data eyes and precursor ISI make this position suboptimal
Solution Approach 1:
The circuit dynamically adjusts the sampling phase away from the fixed one-half bit period position when metastable states are detected. The phase adjust circuit modifies the sampling phase based on metastable detector feedback, allowing the system to adapt to asymmetric data eyes and precursor ISI conditions while maintaining operational simplicity through automated adjustment
Data Source
AI summary
Apparatus(es) and method(s) for CDR are described. In a CDR circuit, there is a bang-bang phase detector (“BBPD”), a baud-rate phase detector (“BRPD”), a multiplexer, and a control circuit. The BBPD, configured to receive data and crossing samples, generates a first result indicating a first phase difference between data and crossing samples. The BRPD, configured to receive data and peak samples, generates a second result indicating a second phase difference between data and peak samples. The multiplexer is configured to select either such result as a phase-detect output for a mode of operation. A control circuit is configured to clear a metastable state: for receipt of the first detect result, check for dithering, determine a direction for phase adjustment responsive to detection of the dithering, and provide a phase adjustment in the direction; and for receipt of the second detect result, operate to use the second phase difference generated.