CDR Out-of-Lock Detection Using Missed Edge Sampling
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Solution Overview
Problem
Current clock-data recovery (CDR) circuits in data communication systems, particularly reference-less designs, face challenges in detecting out-of-lock conditions, including false lock, which can lead to frequency misalignment and data recovery errors.
Innovation Solution
The implementation of out-of-lock detection methods that involve performing frequency and phase acquisition cycles to generate a recovered clock signal, retiming data signals with positive and negative edges, and using edge detection signals to identify missed edges, thereby signaling an out-of-lock condition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If reference-less CDR design is used, then device complexity is reduced, but ability to detect out-of-lock conditions deteriorates
Solution Approach 1:
An edge detection circuit is introduced as an intermediary component that samples the recovered data signal with edges from the received data signal. This mediator detects missed edges and generates signals to indicate out-of-lock conditions, enabling detection capability without adding complex reference clock infrastructure.
Solution Approach 2:
The system uses its own recovered data signal edges to sample and detect out-of-lock conditions. The recovered data signal itself provides the sampling clock for the edge detection circuit, eliminating the need for external reference signals while maintaining self-diagnostic capability.
2Measurement precision
If frequency acquisition loop is added, then frequency alignment accuracy is improved, but device complexity increases
Solution Approach 1:
The frequency detection function is merged into the existing phase-frequency detector (PFD) component. The PFD simultaneously performs both phase detection and frequency detection functions, eliminating the need for a separate frequency acquisition loop while maintaining frequency alignment capability.
Solution Approach 2:
The phase-frequency detector is designed to serve multiple functions: it acts as a phase detector during phase alignment and as a frequency detector during frequency acquisition. This multi-functional approach reduces overall device complexity while maintaining both frequency and phase alignment capabilities.
3Measurement precision
If edge detection sampling is performed, then out-of-lock detection precision is improved, but use of energy increases
Solution Approach 1:
Edge detection sampling is performed periodically at specific critical points (data edges) rather than continuously. The sampling occurs only when transitions in the received data signal are detected, reducing energy consumption while maintaining detection precision through strategic sampling timing.
Solution Approach 2:
Instead of continuously monitoring all signal parameters, the system performs partial sampling only at critical edge transitions. This partial action approach provides sufficient detection precision by focusing resources on the most informative sampling moments when edges occur.
Data Source
AI summary
The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. Out-of-lock detection is accomplished by sampling retimed/recovered data with positive and negative edges of the received data. In example embodiments, an out-of-lock condition is determined either by detecting the occurrence of, or counting, missed edges corresponding to the failure of received data sampling to detect corresponding positive/negative edges of the retimed/recovered data.