CDR Multiplexer and Shared Conversion Stage for Glitch-Free Tracking

Solution Overview

Problem

Existing clock and data recovery (CDR) circuits require dedicated conversion stages for phase and frequency tracking loops, leading to increased circuit area and costs, and suffer from glitches during signal selection.

Innovation Solution

A CDR circuit with a shared conversion stage for both frequency and phase tracking loops, and a multiplexer circuit that synchronizes signal selection with a reference clock signal to reduce glitches, allowing adjustable gains for error signal conversion and reuse of the conversion stage across different operation modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If dedicated conversion stages are used for phase and frequency tracking loops, then tracking precision is improved, but circuit area and manufacturing costs increase

Engineering Contradiction:

Improvetracking precisionVSAvoidcircuit area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent combines the phase tracking loop and frequency tracking loop to share a common conversion stage. The multiplexer circuit allows both tracking loops to use the same conversion stage by selectively connecting either the phase detector or frequency detector to the conversion stage, thereby reducing the total number of conversion stages from two to one while maintaining tracking precision.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The conversion stage is designed to be universal and can perform both phase conversion and frequency conversion functions. By using a multiplexer to selectively connect different detectors (phase detector or frequency detector) to the same conversion stage, the system achieves multi-functionality without requiring separate dedicated conversion stages for each tracking loop.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Measurement precision

If dedicated conversion stages are used for phase and frequency tracking loops, then tracking precision is improved, but manufacturing costs increase

Engineering Contradiction:

Improvetracking precisionVSAvoidmanufacturing costs

Core Design Contradiction:

Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent combines the phase tracking loop and frequency tracking loop to share a common conversion stage. The multiplexer circuit allows both tracking loops to use the same conversion stage by selectively connecting either the phase detector or frequency detector to the conversion stage, thereby reducing the total number of conversion stages from two to one while maintaining tracking precision.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The conversion stage is designed to be universal and can perform both phase conversion and frequency conversion functions. By using a multiplexer to selectively connect different detectors (phase detector or frequency detector) to the same conversion stage, the system achieves multi-functionality without requiring separate dedicated conversion stages for each tracking loop.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If multiplexer circuit switches between different error signals, then operation flexibility is improved, but glitches occur during signal selection

Engineering Contradiction:

Improveoperation flexibilityVSAvoidglitches

Core Design Contradiction:

Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The synchronization circuit performs preliminary action by sampling the selection signal at a first signal edge of the reference clock and generating an enabled signal at a second signal edge of the reference clock. This timing arrangement ensures that the multiplexer switches between error signals only at synchronized clock edges, preventing glitches during signal selection while maintaining operation flexibility.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11411574B2Clock and data recovery circuit with proportional path and integral path, and multiplexer circuit for clock and data recovery circuit

Publication Date: 2022.08.09 M31 TECH

AI summary

A clock and data recovery circuit includes a phase detector (PD), a phase frequency detector (PFD), a multiplexer circuit, a conversion stage and an oscillator. The PD detects a difference in phase between a data signal and an oscillating signal to generate a first set of error signals. The PFD detects a difference in phase and frequency between a reference clock signal and the oscillating signal to generate a second set of error signals. The multiplexer circuit selectively outputs the first set of error signals or the second set of error signals as a third set of error signals according to a selection signal. The conversion stage determines a set of gains according to the selection signal, and converts the third set of error signals with the set of gains to generate a set of input signals. The oscillator generates the oscillating signal according to the set of input signals.