Clock and Data Recovery Circuit with N-Phase Sampling
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Solution Overview
Problem
Current Clock and Data Recovery (CDR) circuits, especially burst mode CDR, are heavily dependent on the jitter of serial data, leading to high jitter in the recovered clock and potential bit errors, especially in high-speed data transmission scenarios.
Innovation Solution
A CDR circuit utilizing an n-phase clock with a sampling and edge detection unit, edge determination unit, clock picking unit, and data picking unit, which performs spaced sampling, edge detection, and filtering to select a clock with the largest phase difference from the n clocks, reducing dependence on serial data jitter by not extracting a clock at each edge occurrence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If burst mode CDR extracts clock at each edge occurrence of serial data, then the circuit structure is simple and suitable for high-speed situations, but the recovered clock jitter becomes high and bit errors occur
Solution Approach 1:
The patent divides the clock recovery process into multiple independent sampling groups (first sampling group, edge detection group, second sampling group) that operate in parallel. Each group processes data independently using different phase clocks, and the results are combined through counting units to produce the final recovered clock. This segmentation allows the system to maintain simplicity while improving reliability.
Solution Approach 2:
The patent performs preliminary sampling of the serial data using multiple phase clocks before the actual clock recovery. The first sampling group samples the serial data at different phases, and the edge detection group detects transitions. This preliminary processing enables the system to have multiple candidate clocks to choose from, reducing the impact of jitter in any single sampling point.
2Reliability
If PLL-based CDR aligns clock edge with data edge using feedback loop, then data synchronization is achieved, but the circuit complexity increases and closed-loop structure is not suitable for high-speed situations
Solution Approach 1:
The patent extracts the clock recovery function from the data sampling function. Instead of using a feedback loop to align clocks (as in PLL), the system independently samples data at multiple phases and uses counting units to determine the optimal sampling point. This extraction eliminates the complex feedback mechanism while maintaining synchronization capability.
Solution Approach 2:
The patent makes the sampling points dynamic by allowing different phases to be selected based on the actual data transitions. The counting units dynamically determine which sampling points correspond to valid data edges, and the clock picking unit dynamically selects the optimal phase for clock recovery. This dynamic adaptation achieves synchronization without requiring complex feedback control.
3Device complexity
If burst mode CDR uses open-loop structure, then the circuit is simpler and more suitable for high-speed situations, but performance becomes heavily dependent on serial data jitter
Solution Approach 1:
The patent merges multiple sampling results into a single recovered clock signal. The first sampling group, edge detection group, and second sampling group all contribute to the same clock recovery process. The counting units combine the sampling results from multiple phases, and the clock picking unit integrates the information to produce a stable recovered clock that is less dependent on any single data transition.
Solution Approach 2:
The counting units serve as intermediaries between the sampling groups and the clock picking unit. They process the sampling results, filter out spurious transitions, and provide a basis for selecting the optimal sampling point. This intermediary processing layer reduces the direct impact of serial data jitter on the recovered clock accuracy.
Data Source
AI summary
The present invention provides a clock and data recovery circuit, including an n-phase clock, a sampling and edge detection unit, an edge determination unit, a clock picking unit and a data picking unit. The sampling and edge detection unit performs spaced sampling on the input serial data using the n-phase clock, and performs edge detection and resampling on the sampled data. The edge determination unit filters the resampled data by the counting units, and obtains the positions of the edges of the serial data according to the counting result of the counting units. The clock picking unit selects a clock from the n clocks that is the farthest away from the edges as the recovered clock. The data picking unit obtains the recovered data according to the recovered clock. The present invention also provides a parallel output circuit.