CDR Phase Detector Offset to Prevent False Lock
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Solution Overview
Problem
High-speed data communication systems face false lock issues in clock and data recovery (CDR) circuits due to frequency mismatches between transmitter and receiver, leading to bit errors, which are difficult to detect and prevent with conventional methods like reducing data path latency.
Innovation Solution
A method that involves adding a pre-defined offset to the phase detector output of a CDR circuit, initializing the frequency loop accumulator with a load value, and determining the lock point to differentiate between real and false locks, with the option to modify or remove the offset once a real lock is confirmed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data path latency is reduced to avoid false lock, then false lock prevention is improved, but there is a limit to how much reduction can be achieved
Solution Approach 1:
The patent applies preliminary action by adding an offset to the phase detector output before the accumulation process occurs. This offset is added in advance to prevent the phase detector output from reaching zero during accumulation, thereby preventing false lock before it can occur. The offset is removed only after successful lock is achieved, maintaining its preventive function throughout the critical accumulation phase.
Solution Approach 2:
The patent changes the parameter of the phase detector output by adding a configurable offset value. This parameter modification shifts the operating point of the phase detector, ensuring that the output remains non-zero during the accumulation process. The offset can be adjusted based on system requirements, providing flexibility in preventing false lock while maintaining normal operation after lock is achieved.
2Reliability
If offset is added to phase detector output to prevent false lock, then false lock prevention is improved, but device complexity increases
Solution Approach 1:
The patent merges the offset addition function with the existing phase detector output path by using a summer circuit that combines the phase detector output with the offset value. This integration approach adds minimal complexity to the existing CDR circuit architecture. The offset removal after lock is achieved by simply setting the offset to zero, further minimizing the complexity increase while maintaining effective false lock prevention.
Data Source
AI summary
An example method of clock and data recovery (CDR) includes adding a pre-defined offset to an output of a phase detector (PD) of a CDR circuit, and loading an accumulator of a frequency loop of the CDR circuit with a pre-defined load value. The method further includes detecting the phase of an incoming signal using a PD, and determining that the CDR has locked onto a real lock point. In some examples, the method further includes determining that the CDR has locked on a real lock point, and, in response to the determination, modifying the pre-defined offset to equal zero.