CDR Lock-to-Reference Circuit Using PFD for Fast VCO Alignment
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits face challenges in maintaining low bit-error-ratio and jitter tolerance due to significant quantization noise from low-resolution control words used in voltage-controlled oscillators, especially in applications with spread spectrum clocks, which increases circuit area, power, and cost.
Innovation Solution
A Phase and Frequency Detector (PFD) based Lock to Reference (L2R) mode is implemented, allowing for rapid frequency and phase alignment of the receiver VCO with a reference clock during data absence, using proportional and integral loop controls to generate control words for the VCO, reducing the need for counter-based methods and minimizing adjustment time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the resolution of the control word applied to the VCO is increased to improve receiver jitter tolerance, then jitter tolerance is improved, but circuit area, power consumption, and cost increase
Solution Approach 1:
The control word is segmented into two parts: a coarse control portion that determines the main frequency steps and a fine control portion that provides precise frequency adjustment. This segmentation allows the system to achieve high resolution frequency control without requiring a fully high-resolution control word, thereby reducing the number of bits needed while maintaining jitter tolerance performance.
Solution Approach 2:
The system dynamically changes the resolution parameter of the VCO control based on operating conditions. During normal operation, a lower resolution is used to minimize area and power, while during lock-to-reference operations or when higher jitter tolerance is required, the effective resolution is increased through the segmented control approach, thus adapting the parameter to match the actual performance requirements.
2Reliability
If the resolution of the control word applied to the VCO is increased to improve receiver jitter tolerance, then jitter tolerance is improved, but power consumption increases
Solution Approach 1:
The control word is segmented into two parts: a coarse control portion that determines the main frequency steps and a fine control portion that provides precise frequency adjustment. This segmentation allows the system to achieve high resolution frequency control without requiring a fully high-resolution control word, thereby reducing the number of bits needed while maintaining jitter tolerance performance.
Solution Approach 2:
The system dynamically changes the resolution parameter of the VCO control based on operating conditions. During normal operation, a lower resolution is used to minimize area and power, while during lock-to-reference operations or when higher jitter tolerance is required, the effective resolution is increased through the segmented control approach, thus adapting the parameter to match the actual performance requirements.
3Measurement precision
If counter-based lock to reference methods are used, then frequency alignment is achieved, but adjustment time is excessive
Solution Approach 1:
The system performs preliminary frequency acquisition using a coarse frequency search mechanism that quickly brings the VCO output close to the reference frequency before engaging the fine frequency adjustment mechanism. This preliminary action eliminates the need for slow counter-based methods by pre-positioning the frequency in the correct range, thereby significantly reducing the overall adjustment time while maintaining accurate frequency alignment.
Solution Approach 2:
The system dynamically switches between different frequency control modes: a fast coarse-tuning mode for initial frequency acquisition and a slow fine-tuning mode for precise frequency alignment. This dynamic adaptation of control bandwidth and resolution allows the system to achieve both rapid frequency acquisition and accurate frequency locking, resolving the contradiction between speed and precision in the lock-to-reference process.
Data Source
AI summary
In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.