CDR Circuit Phase Adjustment for Low-Error Clock Recovery
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits face challenges in accurately detecting signal phase with small phase detection errors without increasing overhead, particularly in high-speed transceivers like the 5-Gbps transceiver, where phase tracking and data determination are performed in the computational domain.
Innovation Solution
A CDR circuit is designed with an analog-to-digital converter, phase adjuster, phase detector, filter, adder, and decision circuit that uses a phase adjuster to modulate the clock signal and perform a filtering process to minimize phase differences, allowing for accurate phase detection without increasing the number of sampling times or bits of the ADC, thereby reducing phase detection errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of sampling times or ADC bits is increased to reduce phase detection errors, then measurement precision improves, but device complexity and overhead increase
Solution Approach 1:
The patent introduces a phase detector as an intermediary component that extracts phase information from the ADC output without requiring additional sampling or increasing ADC resolution. The phase detector processes the existing digital signal to generate phase error information, achieving accurate phase detection without increasing ADC overhead.
Solution Approach 2:
The patent replaces the traditional approach of improving phase detection through increased sampling (mechanical/system resource increase) with a computational domain solution using phase detection algorithms. This substitutes physical resource expansion with signal processing methods, maintaining accuracy while reducing overhead.
2Device complexity
If phase tracking is performed in the computational domain without adjusting sampling clock phase, then device complexity is reduced, but measurement precision deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector continuously monitors the phase relationship between the sampling clock and data signal, and the phase adjuster uses this feedback to dynamically adjust the sampling clock phase. This closed-loop system maintains high measurement precision while keeping the overall device complexity manageable through efficient feedback control.
Solution Approach 2:
The system performs self-adjustment of the sampling clock phase through the phase-locked loop mechanism, where the phase detector and phase adjuster work together to automatically correct phase errors without external intervention. This self-service capability maintains precision while minimizing the need for complex external control circuitry.
Data Source
AI summary
A CDR circuit includes an AD converter that converts an analog input signal to a digital output signal according to an operation clock signal; a phase adjuster that subtracts a first phase from a first clock signal having a first frequency equal to a frequency of the input signal to output a second clock signal having a second frequency as the operation clock signal to the AD converter; a phase detector that detects a second phase in the output signal of the AD converter; a filter that obtains a third phase by performing a filtering process based on the first phase, the second phase, and the third phase output from the filter; an adder that adds the first phase and the third phase to obtain a fourth phase; and a decision circuit that obtains recovered data from the output signal of the AD converter using the fourth phase.