CDR Phase Detector with Adjustable Delay Compensation for Jitter
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Solution Overview
Problem
Conventional CDR circuits face issues with unstable output voltage and increased jitter in the recovered clock due to non-ideal clock-to-output delay in the main D flip-flop, which affects the accuracy of clock data recovery.
Innovation Solution
A phase detector design for CDR circuits that includes adjustable delay circuits, control circuits, and logic circuits to stabilize the output voltage of the charge pump and compensate for non-ideal delays, using HBTD circuits and tuners to fine-tune delay times and control signals for improved clock recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional CDR circuits use a main D flip-flop for clock data recovery, then the circuit structure is simple, but the clock-to-output delay causes non-ideal timing and reduces recovery accuracy
Solution Approach 1:
The invention divides the single D flip-flop into multiple D flip-flops (first D flip-flop, second D flip-flop, third D flip-flop) arranged in a segmented structure. Each flip-flop handles specific timing functions, separating the clock-to-output delay path from the data sampling path. This segmentation eliminates the non-ideal delay effect while maintaining circuit feasibility.
Solution Approach 2:
The invention introduces delay elements as intermediary components between the clock signal and the D flip-flops. These delay elements act as mediators to compensate for the clock-to-output delay, ensuring that the clock signal arrives at the correct timing without requiring complex high-speed flip-flop designs.
2Ease of manufacture
If the charge pump in CDR circuit operates with conventional phase detection, then the circuit is easy to implement, but the output voltage becomes unstable with triangular-waveform characteristics
Solution Approach 1:
The invention implements a feedback mechanism where the phase detector continuously monitors the timing relationship between clock and data signals, and adjusts the delay element settings accordingly. This feedback stabilizes the charge pump output voltage by preventing the triangular-waveform oscillation that occurs in conventional circuits.
Solution Approach 2:
The invention makes the delay elements dynamically adjustable rather than fixed. The delay amount can be tuned based on operating conditions to optimize the phase detection accuracy and stabilize the charge pump output, transforming the static circuit into a dynamically adaptive system.
3Device complexity
If conventional phase detection methods are used, then the detection process is simple, but jitter in the recovered clock increases
Solution Approach 1:
The invention performs preliminary delay adjustment of the clock signal before it reaches the D flip-flops. By pre-compensating for expected delays and jitters through configurable delay elements, the system reduces the impact of timing variations on the final clock recovery, improving reliability without complex real-time correction.
Data Source
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AI summary
A phase detector includes a clock delay circuit, a data delay circuit, a control circuit, a D flip-flop, and a logic circuit. The clock delay circuit delays a clock signal so as to generate a delay clock signal. The data delay circuit delays a data signal so as to generate a delay data signal. The control circuit adjusts the delay time of the clock delay circuit and the delay time of the data delay circuit according to the clock signal and the delay clock signal. The D flip-flop generates a register signal according to the data signal and the clock signal. The logic circuit generates an up control signal and a down control signal according to the data signal, the delay data signal, and the register signal so as to control a charge pump of a CDR (Clock Data Recovery) circuit.