CDR Phase Detector Architecture for Low-Jitter High-Speed Locking
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Solution Overview
Problem
Existing phase detectors for clock and data recovery circuits face challenges in reducing jitter during phase locking, especially at high data rates, with linear detectors producing small but inefficient output jitter and bang-bang detectors generating excessive jitter.
Innovation Solution
A novel phase detector architecture that combines the advantages of linear and bang-bang detectors, utilizing a frequency detector, phase detector, phase charge pump circuit, frequency charge pump circuit, voltage controlled oscillator, and adaptive phase interpolator to generate phase and frequency control signals, reducing jitter and power consumption with a simpler logic design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a linear phase detector is used, then output jitter is reduced, but the narrow pulse may not work well at high data rate
Solution Approach 1:
The phase detector is segmented into multiple independent paths: a linear phase detector path for low-jitter operation and a bang-bang phase detector path for high-speed operation. The system selectively activates appropriate paths based on operating conditions, allowing it to achieve low jitter at high data rates by using the linear path when phase error is small.
Solution Approach 2:
The system dynamically switches between different phase detector operating modes based on real-time conditions. The control circuit monitors the output signals and dynamically enables or disables specific detector paths, allowing the system to adapt its behavior to maintain optimal performance across varying data rates and phase error conditions.
2Speed
If a bang-bang phase detector is used, then it is suitable for high speed circuit operation, but generated jitter is too large
Solution Approach 1:
The phase detector is segmented into multiple independent paths: a linear phase detector path for low-jitter operation and a bang-bang phase detector path for high-speed operation. The system selectively activates appropriate paths based on operating conditions, allowing it to achieve low jitter at high data rates by using the linear path when phase error is small.
Solution Approach 2:
A control circuit acts as an intermediary between the multiple phase detector paths and the charge pump circuit. This intermediary selectively enables or disables specific detector paths based on real-time operating conditions, filtering out the harmful high-jitter characteristic from the bang-bang path when unnecessary, while maintaining its high-speed advantage.
3Reliability
If multiple phase detectors are combined to achieve both low jitter and high speed performance, then device complexity increases
Solution Approach 1:
Multiple phase detector implementations are merged into a single unified circuit structure that shares common components such as the charge pump circuit, voltage controlled oscillator, and feedback paths. This merging reduces overall device complexity compared to implementing separate independent detectors, while still providing the benefits of both linear and bang-bang detection approaches through selective activation.
Data Source
AI summary
A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.