CDR Circuit with Divisor-Controlled Phase Interpolation Range
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Solution Overview
Problem
Conventional clock and data recovery (CDR) circuits face challenges in achieving a wide operation frequency range without degrading linearity due to the limitations of phase interpolator design, where increasing frequency range often reduces linearity and maximum operation speed.
Innovation Solution
The proposed CDR circuit incorporates a phase detector, phase interpolator, finite state machine, and divisor-controllable frequency divider, allowing the phase interpolator to operate at a fixed frequency with high linearity regardless of input data signal frequency, by adjusting the divisor based on the frequency ratio and generating control signals to optimize phase interpolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a switch capacitor array is added at the output terminal to increase operation frequency range, then the operation frequency range is improved, but the linearity and maximum operation speed are reduced due to increased parasitic capacitance
Solution Approach 1:
The frequency division function is segmented from the phase interpolator and implemented by a separate divisor-controllable frequency divider. This segmentation allows the phase interpolator to operate at a fixed optimal frequency for high linearity, while the frequency divider handles the frequency range adaptation by dividing the interpolator's output frequency according to different divisors.
Solution Approach 2:
A divisor-controllable frequency divider is introduced as an intermediary component between the phase interpolator and the phase detector. This intermediary handles the frequency conversion task, allowing the phase interpolator to maintain its optimal operating frequency while still achieving wide frequency range coverage through adjustable division ratios.
2Adaptability or versatility
If the phase interpolator operates frequency is increased to handle higher input frequencies, then the operation frequency range is improved, but the linearity performance is degraded
Solution Approach 1:
The system dynamically adjusts the divisor of the frequency divider based on the input data signal frequency, while the phase interpolator maintains a fixed operating frequency. This dynamic adjustment of the divider ratio allows the system to adapt to different frequency ranges without compromising the linearity of the phase interpolator.
Solution Approach 2:
The divisor parameter of the frequency divider is changed according to the input frequency to maintain the optimal operating frequency of the phase interpolator. By changing the division ratio parameter, the system achieves wide frequency range coverage while keeping the phase interpolator's operating frequency constant for optimal linearity.
Data Source
AI summary
A clock and data recovery (CDR) circuit includes a phase detector, a phase interpolator, a finite state machine, and a divisor-controllable frequency divider. The phase detector compares an input data signal with a frequency dividing signal and generates a phase indication signal to indicate a phase difference between the input data signal and the frequency dividing signal. The phase interpolator performs phase interpolation on first and second clock signals received by the phase interpolator, so as to generate a phase interpolation signal. The finite state machine coupled to the phase detector and the phase interpolator generates the control signal based on the phase indication signal and the phase interpolation signal. The divisor-controllable frequency divider coupled to the phase detector and the phase interpolator divides the second frequency of the phase interpolation signal by a divisor so as to generate the frequency dividing signal. A CDR method is also provided.