CDR Circuit Phase Selection for Fast EEE Clock Resynchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing CDR circuits in terminal devices face challenges in achieving clock synchronization with a peer end within the preset time period, especially when frequency deviations are large, leading to slow convergence and potential data loss during network transitions.
Innovation Solution
A CDR circuit is designed with a state machine, phase detector, phase signal selectors, loop filter, numerical controlled oscillator, and phase signal generator to rapidly implement clock synchronization by generating a phase signal satisfying the preset clock synchronization condition, allowing the terminal to synchronize with the peer end without waiting for loop filter and oscillator convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the CDR circuit uses traditional phase convergence control with two state signals, then the circuit structure is simple, but the convergence speed is slow and clock synchronization cannot be achieved within the preset time period when frequency deviation is large
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing multiple phase adjustment values in a lookup table before the CDR circuit operates. When frequency deviation occurs, the circuit directly retrieves the pre-computed phase adjustment value corresponding to the detected frequency offset, eliminating the need for slow iterative convergence. This allows the circuit to achieve rapid clock synchronization within the 16.5 microsecond REFRESH state period while maintaining relatively simple circuit structure through the use of pre-computed tables rather than complex real-time calculation mechanisms.
2Use of energy by moving object
If the terminal enters QUIET state to save energy, then energy consumption is reduced, but clock synchronization with peer end is lost and requires lengthy re-synchronization
Solution Approach 1:
The patent stores pre-computed phase adjustment values in a lookup table during the ACTIVE state, preparing the synchronization data in advance. When transitioning to the QUIET state, this pre-prepared information enables rapid re-synchronization during the subsequent REFRESH state, minimizing the time lost during state transitions while maintaining energy savings during the QUIET period.
Solution Approach 2:
The patent implements dynamic phase adjustment by using the state machine to select different operational modes based on the current state (ACTIVE, QUIET, REFRESH). During REFRESH state, the circuit dynamically applies the appropriate phase adjustment value from the lookup table to achieve rapid re-synchronization, allowing the system to adapt its behavior to different operational states and minimize synchronization time penalties.
3Measurement precision
If the CDR circuit waits for loop filter and oscillator convergence before synchronization, then phase accuracy is improved, but the synchronization time exceeds the preset period and data transmission is delayed
Solution Approach 1:
The patent pre-computes and stores phase adjustment values for various frequency offset scenarios in a lookup table during the ACTIVE state. When entering the REFRESH state, the circuit retrieves the appropriate pre-computed value based on the detected frequency offset and applies it immediately, achieving both acceptable phase accuracy and rapid synchronization within the 16.5 microsecond period, eliminating the need to wait for traditional loop filter and oscillator convergence.
Data Source
AI summary
Embodiments of the present invention disclose a CDR circuit and a terminal, where the CDR circuit is configured to perform clock synchronization in a terminal with EEE function, and the CDR circuit includes: a phase detector, a first phase signal selector, a loop filter, a numerical controlled oscillator, a second phase signal selector, a phase signal generator, and a state machine. In the embodiments of the present invention, after the terminal enters a REFRESH state from a QUIET state, the CDR circuit can implement clock synchronization with a peer end without waiting for the loop filter and the numerical controlled oscillator to be converged, but the phase signal generator generates a phase signal satisfying a preset clock synchronization condition, and the second phase signal selector selects the phase signal satisfying the preset clock synchronization condition as the phase selection signal of the CDR.