CDR Circuit Phase Filter With Auxiliary Signal for Low Latency
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Solution Overview
Problem
Conventional digital-based clock and data recovery (CDR) circuits suffer from long loop latency due to speed limitations in semiconductor processes, making them unsuitable for high-speed applications.
Innovation Solution
A CDR circuit design incorporating a first phase detector, controller, and phase filter with a second path utilizing an auxiliary signal to reduce overall latency, where the phase detector generates a control signal and an auxiliary signal to adjust the clock signal, effectively minimizing loop latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a digital controller is used in the conventional Digital-based CDR circuit, then the circuit can be implemented using conventional semiconductor processes, but the loop latency becomes long due to speed limitations
Solution Approach 1:
The CDR circuit is segmented into two parallel paths: a first path containing the digital controller for standard implementation, and a second path containing a phase detector and auxiliary signal generation for fast latency reduction. This segmentation allows each path to optimize for its specific function while working together to solve the overall latency problem.
Solution Approach 2:
An auxiliary signal is introduced as an intermediary element that carries phase detection information from the input signal directly to the phase filter in the second path. This intermediary enables fast latency reduction by bypassing the slow digital controller while still providing accurate phase information for clock signal adjustment.
2Loss of time
If the speed of the digital controller is increased to reduce loop latency, then the latency is reduced, but the semiconductor process complexity increases
Solution Approach 1:
Instead of speeding up the digital controller, the patent creates a parallel copy path (second path) that performs phase detection and auxiliary signal generation. This copy path uses simpler, faster components that can operate at lower process complexities while achieving the same latency reduction goal.
Solution Approach 2:
The system dynamically switches between or combines information from both paths: the first path provides stable, manufacturable operation while the second path provides fast latency reduction. The phase filter integrates information from both paths to generate the final clock signal, allowing the system to adaptively use the appropriate path based on operational requirements.
Data Source
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AI summary
The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.