CDR Phase Filtering for High-Speed I/O Clock Recovery
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Solution Overview
Problem
Existing systems for recovering a clock signal in source-synchronous digital data are sensitive to environmentally induced frequency and phase changes, as well as random bit patterns, leading to inaccurate phase corrections and increased bit-error-rate (BER).
Innovation Solution
A data receiver system that includes a clock generator and phase filter circuitry using an up/down counter to measure phase differences, apply phase corrections, and adjust the clock phase, while minimizing sensitivity to random bit patterns through configurable threshold settings and blanking intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase error signals are used to adjust the phase of the recovered clock, then the phase accuracy is improved, but the system becomes sensitive to random bit patterns causing false phase corrections
Solution Approach 1:
The patent introduces an intermediary filtering mechanism between the phase error signal generation and the clock phase adjustment. The filter accumulates phase error samples over multiple clock cycles and only applies correction when the accumulated error exceeds a threshold, thereby mediating between raw phase errors and actual corrections to eliminate sensitivity to random bit patterns
Solution Approach 2:
The system performs preliminary accumulation and threshold comparison of phase errors before applying any phase correction. By pre-processing the phase error signals through accumulation and thresholding, the system ensures that only significant, persistent phase errors trigger corrections, preventing premature or false corrections due to random bit patterns
2Reliability
If phase error signals are filtered to reduce sensitivity to random bit patterns, then reliability is improved, but the response to environmental changes may be delayed
Solution Approach 1:
The filtering mechanism is designed to be dynamic rather than static. The accumulation window and threshold parameters can be adjusted based on operating conditions, allowing the system to adapt its filtering aggressiveness. This enables the system to maintain reliability by filtering random patterns while preserving speed by reducing filtering when environmental changes are detected
Solution Approach 2:
The system changes the parameters of the filtering operation based on the characteristics of the incoming phase error signals. By monitoring the rate of phase errors and the magnitude of accumulated errors, the system adjusts filtering parameters to optimize the balance between reliability (filtering out noise) and speed (responding to real changes)
3Stability of the object's composition
If the sampling point is moved closer to bit transitions to increase timing margin, then the timing margin is improved, but the bit-error-rate increases due to jitter
Solution Approach 1:
The patent implements a feedback mechanism where the phase error signal is continuously generated by comparing the timing of data transitions with the recovered clock. This feedback loop allows the system to dynamically adjust the sampling point to maintain optimal timing margin while compensating for jitter through continuous phase correction
Data Source
AI summary
A data receiver system. The system includes a clock generator configured to output a reference clock and circuitry configured to measure a direction of a phase difference between an input data stream and the reference clock. The circuitry is further configured to increment a counter if the phase difference is in a first direction, decrement the counter if the phase difference is in a direction opposite to the first direction, and convey a phase correction signal to the clock generator if an output value of the counter meets or exceeds a threshold. The clock generator is configured to adjust the phase of the reference clock in response to receiving the phase correction signal.