Clock Data Recovery Filter With Fast Phase and Slow Frequency Loops
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Solution Overview
Problem
Clock data recovery (CDR) circuits face latency issues in anticipating phase and frequency changes in serial data signals, especially when transitions are infrequent, leading to suboptimal synchronization and increased data errors.
Innovation Solution
A second-order digital filter is used with separate feedback loops for phase and frequency control, where the phase responsive loop operates at a faster rate than the frequency responsive loop, allowing for anticipatory control of clock signal regeneration based on early/late phase comparisons and accumulated frequency information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a second-order digital filter uses separate feedback loops for phase and frequency control, then the control can respond to both phase error and accumulating phase error (frequency error), but the latency of the control loop increases because frequency information requires accumulation of multiple early/late phase comparison bits
Solution Approach 1:
The patent divides the second-order digital filter into two separate feedback loops: a phase feedback loop that processes early/late comparisons at a first (faster) rate, and a frequency feedback loop that accumulates these comparisons at a second (slower) rate. This segmentation allows each loop to operate independently at its optimal rate, reducing overall control latency while maintaining the ability to correct both phase and frequency errors.
Solution Approach 2:
The patent implements dynamic operation rates for the two feedback loops, with the phase loop operating faster than the frequency loop. This dynamic approach allows the system to respond quickly to phase transitions while still maintaining accurate frequency tracking through accumulated measurements, optimizing the trade-off between responsiveness and measurement accuracy.
2Stability of the object's composition
If the controllable oscillator or delay remains stable at the last known frequency/phase condition when no data transitions occur, then stability is maintained, but the ability to anticipate the timing of the next transition is reduced
Solution Approach 1:
The patent applies preliminary action by having the phase feedback loop continuously adjust the oscillator or delay based on early/late comparisons before actual data transitions occur. This allows the system to anticipate and prepare for upcoming transitions, improving synchronization accuracy without sacrificing stability during periods without transitions.
Solution Approach 2:
The patent implements continuous feedback through the phase feedback loop that monitors early/late comparisons and adjusts the oscillator or delay in real-time. This feedback mechanism allows the system to adapt to changing conditions and anticipate transitions while maintaining stability through controlled adjustments rather than abrupt changes.
3Productivity
If the phase feedback loop operates at a higher repetition rate than the frequency feedback loop, then control latency is reduced and responsiveness is improved, but the device complexity increases due to the hybrid operating rates
Solution Approach 1:
The patent segments the feedback control system into two distinct loops with different operating rates, allowing each to be optimized independently. The phase loop operates at a higher rate for quick corrections, while the frequency loop operates at a lower rate for stable accumulation, reducing the need for complex coordination mechanisms that would otherwise be required in a single-loop system.
Solution Approach 2:
The patent merges the outputs of the two feedback loops (phase correction and frequency correction) into a unified control signal for the oscillator or delay. This combining approach simplifies the overall system architecture by maintaining separate processing paths for efficiency while using a single control interface, reducing device complexity despite the hybrid operating rates.
Data Source
AI summary
A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.