CDR Phase Interpolator With Active Integrators for Linear Clock Transitions
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Solution Overview
Problem
Current clock and data recovery (CDR) circuits face challenges in optimizing phase interpolation, leading to suboptimal signal shaping and linearity of the output clock signal, particularly in decoding high data rate serial data streams without a separate clock signal.
Innovation Solution
A phase interpolator with cross-coupled differential amplifier stages and current steering control, coupled with active integrators, is used to produce an output signal with transitions occurring between the level transitions of two input signals, ensuring smooth and linear transitions by extending the overlap of input signal rise times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase interpolation is used to achieve fine phase adjustment between clock subdivisions, then phase resolution is improved, but signal shaping quality and linearity deteriorate
Solution Approach 1:
An intermediary linearization circuit is introduced between the phase interpolator and the output to reshape the interpolated clock signal. This circuit includes transmission gates and current sources that work together to linearize the transition regions of the phase-interpolated signal, thereby improving signal shaping quality while preserving the fine phase resolution achieved through interpolation.
Solution Approach 2:
The patent dynamically adjusts circuit parameters including current levels and timing characteristics to optimize both phase resolution and signal linearity. By controlling the current steering ratios and timing of transmission gates, the system maintains accurate phase interpolation while compensating for non-linearities in the output signal transitions.
2Device complexity
If simple phase interpolation is used, then device complexity is reduced, but output signal linearity and smoothness deteriorate
Solution Approach 1:
A linearization circuit acts as an intermediary stage that processes the output of a relatively simple phase interpolator. This circuit uses transmission gates controlled by phase signals and current sources to reshape the output waveform, adding minimal complexity while significantly improving signal linearity and smoothness.
Solution Approach 2:
The patent replaces complex mechanical or highly circuitous approaches to signal linearization with a streamlined electronic implementation using transmission gates and current mirrors. This substitution achieves effective waveform shaping with reduced device complexity compared to traditional methods.
3Reliability
If phase transitions are sharply defined, then clock signal integrity is improved, but transition overlap between input signals is reduced
Solution Approach 1:
The linearization circuit performs preliminary shaping of the phase transitions before they are used for data sampling. By pre-linearizing the transition regions and extending their duration through controlled current steering, the circuit ensures that sufficient overlap exists between input signal transitions while maintaining the integrity and sharpness of the final output clock edges.
Solution Approach 2:
The patent dynamically controls the timing and duration of transition overlap using current-steering mechanisms and gated current sources. The circuit adjusts the effective transition width and timing based on the relative phases of input signals, maintaining optimal overlap conditions dynamically while preserving output signal integrity.
Data Source
AI summary
A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.