CDR Clock Phase Shifting to Resolve Meta-Stable Locking
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Solution Overview
Problem
High-speed data communication systems face meta-stability issues in clock and data recovery circuits, leading to prolonged lock times due to indecisive phase detection, which can be exacerbated by external interference.
Innovation Solution
The solution involves generating data and crossing samples from a received signal, adjusting the phase of the sampling clock based on these samples, and temporarily altering the relative phase between data and crossing clocks from a first phase difference to a second phase difference less than ninety degrees, before reverting back to the original phase after a threshold time, to facilitate quicker locking and avoid meta-stable conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data sampling phase falls at the crossing area when the system starts, then the CDR circuit can eventually lock to the correct phase, but the lock time becomes excessively long due to meta-stability
Solution Approach 1:
The patent applies preliminary action by temporarily shifting the phase relationship between data and crossing clocks before the CDR locking process begins. The clock manager circuit proactively adjusts the phase difference from the standard 90 degrees to a non-90 degree phase difference, which prevents the phase detector from entering a meta-stable state. This preliminary phase adjustment is made before the data samples and crossing samples are used for phase detection, thereby avoiding the prolonged lock time issue while ensuring the CDR can eventually achieve accurate locking.
2Adaptability or versatility
If the phase detector operates in meta-stable condition, then external interference can eventually push the CDR to lock, but the phase detection becomes indecisive and lock time increases
Solution Approach 1:
The patent applies preliminary anti-action by preemptively preventing the meta-stable condition through phase relationship adjustment. Instead of allowing the phase detector to enter an indecisive meta-stable state and then relying on external interference to resolve it, the clock manager circuit proactively shifts the phase difference between data and crossing clocks to a non-90 degree value. This preliminary anti-action eliminates the harmful meta-stable condition before it can affect locking speed, while still allowing the CDR to respond to external interference for phase adjustments during normal operation.
3Stability of the object's composition
If the relative phase between data clock and crossing clock is maintained at 90 degrees, then the CDR circuit operates normally, but meta-stable conditions occur that prolong locking time
Solution Approach 1:
The patent applies dynamics by making the phase relationship between data and crossing clocks adjustable rather than fixed. The clock manager circuit dynamically changes the phase difference from the standard 90 degrees to a non-90 degree phase difference during specific operational conditions (such as during locking or when meta-stability is detected). This dynamic adjustment allows the system to optimize performance by temporarily altering the phase relationship to prevent meta-stability, while maintaining normal 90-degree operation during stable locked states.
Data Source
AI summary
An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.