Clock Data Recovery Circuit Phase Calibration
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Solution Overview
Problem
Conventional clock and data recovery (CDR) systems face challenges in minimizing clock skew between different channels, leading to errors in data alignment due to phase shifts, which increases device size and hampers miniaturization with the use of large delay locked loops and extensive logic circuits.
Innovation Solution
The proposed solution involves a data communication system with a CDR circuit and phase control circuit that uses training patterns with extended clock periods to detect phase differences and provide control codes for delay circuits, allowing for phase calibration and synchronization, thereby reducing clock skew without the need for large memory and logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay locked loop and large memory are employed to alleviate clock skew, then clock synchronization accuracy is improved, but device size increases
Solution Approach 1:
The patent extracts the clock skew compensation function from the traditional delay locked loop and separates it into per-channel delay circuits controlled by phase control circuits. This extraction allows for more efficient resource utilization and reduced overall device size while maintaining synchronization accuracy.
Solution Approach 2:
The patent implements dynamic phase control where phase control circuits adjust delay values in real-time based on detected phase differences between channels. This dynamic adjustment mechanism replaces the static, memory-intensive approach of traditional delay locked loops, enabling accurate clock skew compensation with reduced device size.
2Reliability
If 8B/10B encoding scheme is used to ensure data reliability, then data transfer reliability is improved, but transmission overhead increases
Solution Approach 1:
The patent changes the encoding parameters by transitioning from 8B/10B encoding to 6B/8B encoding scheme. This parameter change maintains data reliability through improved error detection and correction capabilities while reducing the overhead from 25% to 20%, thereby increasing effective data throughput.
Data Source
AI summary
A data communication system comprising a first transmitter set configured to transmit a first output based on a first signal, the first output including one of a training pattern and a first data, the training pattern and the first data including clock information, a second transmitter set configured to transmit a second output based on the first signal, the second output including one of the training pattern and a second data, a first receiver set configured to generate a first received data based on the first output, a second receiver set configured to generate a second received data based on the second output, a clock and data recovery (CDR) circuit configured to extract the clock information based on the first signal and the first received data and provide a second signal indicating whether a frequency in-lock status is reached, a phase control circuit in the second receiver set, the phase control circuit being configured to detect a phase difference between the first received data and the second received data and provide a third signal indicating whether a phase in-lock status is reached, and a detector configured to generate the first signal based on the second signal and the third signal.