CDR Phase Step Switching for Wider Frequency Tracking
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Solution Overview
Problem
Clock data recovery (CDR) circuits face challenges in maintaining sufficient frequency tracking range while minimizing power consumption and phase quantization error, especially at higher data signal frequencies, as increasing phase update period reduces tracking range and increasing phase step size increases error.
Innovation Solution
A method and apparatus for adjusting the phase step size of a CDR circuit using a phase step adjuster and controller, dynamically switching between two phase step paths based on frequency offset, with a sigma-delta modulator controlling the phase step size to increase tracking range while reducing quantization noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the phase update period is increased to reduce power consumption, then power consumption is reduced, but the frequency tracking range is reduced
Solution Approach 1:
The patent implements dynamic adjustment of the phase step size based on the detected frequency offset. When frequency offset is large, a larger phase step size is applied to expand tracking range. When frequency offset is small, a smaller phase step size is used to reduce quantization error. This dynamic adaptation resolves the contradiction by making the system flexible rather than fixed.
Solution Approach 2:
The patent changes the phase step size parameter dynamically based on operating conditions (frequency offset). By adjusting this critical parameter, the system can operate efficiently across different frequency conditions, achieving both low power consumption and adequate tracking range when needed.
2Adaptability or versatility
If the phase step size is increased to increase tracking range, then frequency tracking range is increased, but phase quantization error is increased
Solution Approach 1:
The system dynamically adjusts phase step size based on the magnitude of frequency offset. When frequency offset is large, a larger phase step size is tolerated to maintain tracking capability. When frequency offset is small, the system switches to a smaller phase step size to minimize quantization error, thus achieving both goals at different operating points.
Solution Approach 2:
Different phase step sizes are applied locally based on the specific operating condition (frequency offset magnitude). The system uses small phase step sizes in normal operating conditions for precision, and large phase step sizes only when necessary for tracking, thus maintaining high precision while preserving tracking range.
3Adaptability or versatility
If the phase update period is decreased to increase tracking range, then frequency tracking range is increased, but power consumption is increased
Solution Approach 1:
Rather than continuously updating phase at high frequency, the system dynamically adjusts the phase step size magnitude based on frequency offset. This allows the system to maintain adequate tracking range with less frequent updates, reducing power consumption while preserving tracking capability when needed.
Data Source
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AI summary
Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).