CDR Phase Interpolator Walking to Prevent Reset Timing Violations
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Solution Overview
Problem
Existing clock data recovery (CDR) circuits in programmable ICs face timing violations due to sudden changes in phase interpolator codes during reset operations, which can lead to system failures.
Innovation Solution
Implementing a synchronous phase walking mechanism that gradually adjusts the offset between data and crossing phase interpolator codes, either by stepping the crossing code while holding the data code constant or by incrementing/decrementing both codes together, to avoid sudden changes and satisfy preset criteria.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If phase interpolator codes are suddenly changed during reset operations, then reset functionality is achieved, but timing violations occur in clock dividers
Solution Approach 1:
The patent applies preliminary action by performing a synchronous phase walk before normal CDR operation to gradually adjust phase interpolator codes to their target values. This preparatory step ensures that when reset operations occur, the codes are already in a stable state, preventing timing violations in clock dividers while maintaining proper reset functionality.
Solution Approach 2:
The patent implements dynamics by transitioning from static phase interpolator codes to dynamically adjusted codes through synchronous phase walking. During reset, instead of sudden code changes, the system dynamically adjusts codes in a controlled manner, allowing clock dividers to adapt smoothly and avoid timing violations while still achieving reset objectives.
2Reliability
If phase interpolator codes are gradually adjusted through synchronous phase walking, then timing violations are prevented, but reset operation time increases
Solution Approach 1:
The patent applies segmentation by dividing the phase adjustment process into distinct phases: a synchronous phase walk phase that occurs periodically to gradually adjust codes, and a normal operation phase where codes are stable. This segmentation allows the system to spend minimal time in the gradual adjustment mode while still achieving reliable timing violation prevention, thus reducing the overall time loss compared to continuous gradual adjustment.
3Productivity
If phase interpolator codes are suddenly changed, then reset is achieved quickly, but system reliability decreases due to timing violations
Solution Approach 1:
The patent implements periodic action by performing synchronous phase walks at specific intervals or under specific conditions rather than continuously. This periodic adjustment maintains phase interpolator codes in a valid range, preventing timing violations and ensuring system reliability, while allowing quick reset operations to occur between periodic adjustments when sudden changes are safe.
Data Source
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AI summary
Methods and apparatus are described for synchronously stepping at least one of a data phase interpolator (PI) code (306) or a crossing PI code (308) in a clock and data recovery (CDR) circuit (206) until one or more preset criteria are satisfied. One example method generally includes determining (502) that a condition has been met; based on the determination, stepping (504), in a CDR circuit (206), at least one of a data PI code (306) or a crossing PI code (308) for each cycle of a clock (302); stopping (506) the stepping based on one or more criteria to generate a predetermined state of the data PI code (306) and the crossing PI code (308), wherein the predetermined state comprises an offset between the data PI code (306) and the crossing PI code (308); receiving (508) a data stream (218); and performing (510) clock and data recovery on the data stream (218) based on the offset between the data PI code (306) and the crossing PI code (308).