CDR PLL Frequency Training for Low-Power PON Wake-Up
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Solution Overview
Problem
Conventional clock and data recovery units in PON systems experience significant power wastage during standby modes, particularly in 10 Gbps-class optical network units, leading to inefficient power consumption and potential communication failures upon activation.
Innovation Solution
Incorporating a reference clock multiplier circuit, a phase-locked loop with a voltage-controlled oscillator, and a frequency training loop that can transition between power-saving and normal modes, allowing for synchronous oscillation training using the reference clock multiplier circuit before the phase-locked loop enters normal mode, and enabling power-saving by stopping unnecessary components during idle periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the phase-locked loop is kept in normal operable state to ensure stable communication upon activation, then communication reliability is improved, but power consumption increases
Solution Approach 1:
The frequency training loop performs preliminary frequency training of the voltage-controlled oscillator using the reference clock multiplier circuit before the phase-locked loop is activated. This preliminary action prepares the oscillator in advance, reducing the time needed for stable operation once activated, thereby allowing the system to spend more time in power-saving mode while maintaining reliability.
Solution Approach 2:
The system dynamically transitions between power-saving mode and normal operable state based on communication needs. The phase-locked loop and frequency training loop are selectively activated only when communication is required, optimizing the balance between power consumption and communication reliability.
2Loss of energy
If the optical network unit is placed in halt state to reduce power consumption, then power saving is improved, but communication stability deteriorates
Solution Approach 1:
Before the optical network unit transitions from halt state to active state, the frequency training loop performs preliminary frequency training of the voltage-controlled oscillator. This ensures that when communication starts, the oscillator is already frequency-synchronized, preventing communication failures and maintaining stability while allowing extended halt periods for power saving.
Solution Approach 2:
The clock and data recovery unit is segmented into distinct functional blocks: the reference clock multiplier circuit, the frequency training loop with voltage-controlled oscillator, and the phase-locked loop. This segmentation allows selective activation of components - the frequency training loop can be activated for preliminary training while the main phase-locked loop remains inactive during halt state, enabling power saving without compromising communication stability.
3Measurement precision
If the frequency training loop operates continuously to maintain synchronization, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The frequency training loop operates periodically rather than continuously - it performs frequency training before activation from halt state and can be reactivated if communication conditions change. This periodic operation maintains synchronization accuracy when needed while minimizing power consumption during normal operation and halt state.
Solution Approach 2:
The system dynamically controls the operation of the frequency training loop based on communication state. The loop is activated when transitioning from halt state or when communication conditions require re-synchronization, and deactivated when communication is stable or during halt state, optimizing the balance between synchronization accuracy and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces wasted power consumption and enables rapid, secure communication by optimizing power usage and synchronization times within the clock and data recovery unit.
Implementation Method 1
those devices involved in phase-lock control for clock and data recovery
Implementation Method 2
a reference clock multiplier circuit that multiplies a reference clock signal and outputs a multiplied reference clock signal
Data Source
AI summary
In the present invention, wasted power consumption caused when a clock and data recovery unit in an optical network unit in a PON system is activated from a power-saving state is reduced and rapid, secure communication is performed. A clock and data recovery unit includes a phase-locked loop that can be set to normal mode or power-saving mode and that includes a voltage-controlled oscillator and recovers a clock signal and a data signal from input signals. The clock and data recovery unit includes a reference clock multiplier circuit that multiplies a reference clock signal and outputs the multiplied reference clock signal; and a frequency training loop that includes the same voltage-controlled oscillator and performs synchronous oscillation training by the voltage-controlled oscillator using the reference clock multiplier circuit before the phase-locked loop transitions from power-saving mode to normal mode.