CDR PLL Proportional Path Calibration for Jitter Tolerance
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Solution Overview
Problem
The phase-locked loop (PLL) circuit in clock data recovery (CDR) systems for semiconductor memory devices faces challenges in maintaining high frequency characteristics and jitter tolerance due to characteristic fluctuations, which affect data transmission reliability.
Innovation Solution
The implementation of a receiving device with a PLL circuit that includes a current control oscillator, phase detector, integral path, and proportional path, where the proportional path is calibrated to adjust the second current based on frequency-current characteristics, improving high frequency characteristics and jitter tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the PLL circuit operates at high frequency to achieve high data transmission rate, then the data transmission rate is improved, but the high frequency characteristics deteriorate due to characteristic fluctuation
Solution Approach 1:
The patent adjusts the proportional path coefficient (Kp) as a variable parameter to optimize PLL performance. By dynamically changing the Kp value based on operating conditions, the system maintains high frequency characteristics while operating at high data transmission rates, resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the PLL circuit monitors its own performance characteristics and adjusts the proportional path coefficient accordingly. This closed-loop control ensures that high frequency characteristics are maintained even when operating conditions change, allowing reliable high-speed data transmission.
2Reliability
If the PLL circuit increases jitter tolerance to ensure reliable data extraction, then the jitter tolerance is improved, but the high frequency characteristics deteriorate
Solution Approach 1:
The patent independently optimizes the proportional path coefficient (Kp) to achieve both high jitter tolerance and high frequency characteristics. By treating Kp as an adjustable parameter rather than a fixed value, the system can simultaneously improve reliability against jitter while maintaining precise high-frequency operation.
Solution Approach 2:
The patent makes the proportional path coefficient dynamic rather than static. The Kp value can be adjusted based on the operating state, allowing the PLL to adapt to different jitter conditions while maintaining high frequency characteristics. This dynamic adjustment resolves the contradiction between robustness and precision.
3Device complexity
If the PLL circuit uses fixed proportional path coefficient to simplify design, then the device complexity is reduced, but the high frequency characteristics fluctuate
Solution Approach 1:
The patent introduces a可调 (adjustable) proportional path coefficient that can be programmed or configured based on the specific application requirements. This approach maintains relative design simplicity while enabling optimization of high frequency characteristics for different operating conditions, resolving the contradiction between simplicity and stability.
Data Source
AI summary
A receiving device includes a phase-locked loop (PLL) circuit having a current control oscillator, a phase detector, an integral path, and a proportional path. The current control oscillator can generate an oscillation clock based on a first and second current. The phase detector can acquire a phase detection result based on the oscillation clock and a received signal. The integral path can generate the first current based on an integrated value of the phase detection results and supply the first current to the current control oscillator. The proportional path includes a digital-to-current converter to generate the second current based on the phase detection result and supply the second current to the current control oscillator. The receiving device includes a controller configured to adjust the second current based on frequency-current characteristics of the current control oscillator.