CDR PLL Behavioral Simulation for Jitter and PPM Tracking
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Solution Overview
Problem
Current simulation models for clock-data recovery (CDR) phase-locked loops (PLLs) face challenges in accurately modeling signal noise, particularly jitter and parts-per-million (PPM) errors, while balancing complex simulation features with fast runtime and abstraction, and struggle to efficiently recover from noisy signals.
Innovation Solution
A simulation model that filters data and reference clock signals to remove jitter and PPM errors using a threshold function, adjusts the reference clock signal based on data signal phases, and updates prediction models to align phases, applying a delay to the reference clock to account for lag, thereby ensuring accurate and efficient simulation of CDR PLLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If simulation models include complex features to accurately model jitter and PPM errors, then measurement precision is improved, but simulation runtime increases
Solution Approach 1:
The simulation model is segmented into distinct functional blocks: a phase detector block that measures phase differences, a jitter modeling block that introduces controlled random variations, and a PPM error modeling block that applies frequency offsets. This segmentation allows each block to be optimized independently, maintaining accuracy while improving overall simulation efficiency through modular computation.
Solution Approach 2:
The invention uses simplified analytical models that copy the essential behavior of complex analog PLL circuits. Instead of fully simulating continuous-time analog waveforms, the model copies the key phase detection and loop filtering behaviors using discrete mathematical relationships, achieving comparable accuracy with significantly reduced computational overhead.
2Productivity
If simulation models provide sufficient abstraction for fast runtime, then productivity is improved, but measurement precision deteriorates
Solution Approach 1:
The model dynamically adjusts parameters based on operating conditions. The phase detector uses different measurement strategies depending on whether the PLL is locked or unlocked, and the jitter/PPM models adjust their statistical parameters based on the current loop bandwidth and operating frequency. This parameter adaptation maintains precision across different simulation scenarios while keeping computations efficient.
3Adaptability or versatility
If the simulation model tracks both data and reference clock signals, then adaptability is improved, but device complexity increases
Solution Approach 1:
The phase detector block is designed as a universal component that can process both data signal edges and reference clock edges through the same computational pathway. By using a unified phase measurement approach that accepts any input signal edge, the model achieves multi-functionality without duplicating logic, thereby reducing overall device complexity while maintaining the ability to track both signal types.
Data Source
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AI summary
Method and non-transitory computer-readable medium storing instructions for simulating a phase-locked loop measures a first phase of a data signal and a second phase of a reference clock signal in a phase-locked loop to be simulated, filters the first phase of the data signal by a threshold function of a lock detection module of the phase-locked loop to be simulated, and adjusts the second phase of the reference clock signal to align with the filtered first phase of the data signal.