CDR Reference Voltage Control for Jitter-Tolerant USB Type-C
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Solution Overview
Problem
Conventional phase locked loop (PLL) or delay locked loop (DLL)-based clock and data recovery circuits struggle with jitter, frequency drift, and ground shifting in USB Type-C communication, making it difficult for receivers to recover the clock and retime data effectively, especially due to the lack of a reference clock and limited phase track capability.
Innovation Solution
A method involving determining the power mode of a device and setting reference voltage levels based on that mode, using these levels for comparison against incoming data to recover the clock signal, and employing time-to-digital converters (TDCs) and a digitally controlled oscillator (DCO) to generate a recovery clock signal, while dynamically controlling the reference voltage to minimize noise and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PLL or DLL-based CDR circuit is used, then the circuit can operate without a reference clock, but it cannot properly recover the clock signal due to jitter, frequency drift and ground shifting
Solution Approach 1:
The patent dynamically adjusts the reference voltage level based on detected signal conditions (jitter, frequency drift, ground shifting). By changing the voltage parameter adaptively, the comparator can maintain optimal decision thresholds despite signal degradation, enabling reliable clock recovery in USB Type-C communication without a reference clock
Solution Approach 2:
The system continuously monitors the incoming data signal quality and uses this feedback to adjust the reference voltage level in real-time. This closed-loop approach allows the CDR circuit to compensate for jitter and frequency drift by adapting its decision threshold based on actual signal conditions
2Reliability
If a conventional CDR circuit is used, then the circuit area and power consumption are reduced, but the phase track capability is slow and cannot handle fast events like cycle-to-cycle jitter
Solution Approach 1:
The patent implements dynamic reference voltage adjustment that can respond quickly to fast phase events. By making the reference voltage可调 (adjustable) rather than fixed, the system gains the ability to track fast phase changes without requiring a complex, large-scale circuit design
Solution Approach 2:
The system applies local optimization by adjusting only the reference voltage parameter that is most critical for handling fast phase events, rather than redesigning the entire CDR circuit. This localized approach improves phase tracking speed while maintaining overall circuit simplicity
3Reliability
If the reference voltage level is fixed, then the circuit design is simpler, but the noise immunity is reduced in varying power modes
Solution Approach 1:
The patent changes the reference voltage parameter based on the detected power mode (source mode, sink mode, or neutral mode). This adaptive approach improves noise immunity by optimizing the comparator threshold for each specific operating condition, while the complexity is managed through a systematic voltage selection approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient clock and data recovery in noisy environments with reduced power consumption and area, ensuring high accuracy of the recovered clock signal and improved noise immunity.
Implementation Method 1
using at least one of the first reference voltage level and the second reference voltage level for comparison against incoming data
Data Source
AI summary
In one aspect, a method includes: determining a power mode of a device; setting a first reference voltage level and a second reference voltage level based at least in part on the power mode; and using at least one of the first reference voltage level and the second reference voltage level for comparison against incoming data.