Clock and Data Recovery Sampling Offset Correction for High-Speed Links
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Solution Overview
Problem
Current clock and data recovery circuits face challenges in accurately recovering high-speed serial transmissions due to limitations in integrated circuit fabrication techniques, which result in difficulties in achieving precise alignment and sufficient bandwidth, leading to excessive jitter and noise, and are cost-prohibitive for high-speed serial transceivers.
Innovation Solution
A clock and data recovery circuit with sampling offset correction, comprising an input section, pulse generator, charge pump, loop filter, voltage controlled oscillator, and sample position adjust module, adjusts the sampling position based on transition information to correct sampling offset and reduce noise, enabling accurate data and clock recovery from high-speed serial transmissions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed serial transmissions are processed using conventional clock and data recovery circuits, then data rate increases, but sampling alignment precision deteriorates due to fabrication limitations
Solution Approach 1:
The patent applies preliminary action by detecting sampling offset before it causes data errors, using a phase detector to measure the offset between the sampling clock and data transitions, then pre-correcting this offset by adjusting the sampling clock phase to prevent misalignment from occurring in the first place
Solution Approach 2:
The patent implements feedback by continuously monitoring the alignment between sampling clock edges and data transitions using a phase detector, then feeding this information back to a sampling offset corrector that adjusts the sampling clock phase to maintain optimal alignment, creating a closed-loop control system
2Device complexity
If conventional clock and data recovery circuits are used, then device complexity remains low, but noise and jitter increase due to insufficient bandwidth
Solution Approach 1:
The patent introduces an intermediary element - a dedicated sampling offset corrector block - that acts as a mediator between the phase detector and the sampling register, specifically designed to compensate for sampling timing errors without requiring a complete redesign of the entire clock and data recovery circuit
3Speed
If alternative IC fabrication processes (silicon germanium or gallium arsenide) are used to achieve greater speeds, then operating speed increases, but manufacturing cost increases substantially
Solution Approach 1:
The patent changes the parameter being controlled from the fabrication process material to the sampling clock phase timing, allowing high-speed operation through precise timing adjustment rather than through expensive alternative semiconductor materials, thus achieving speed improvement through parameter optimization rather than material substitution
Data Source
AI summary
A method for correcting sampling offset of a clock and data recovery circuit begins for consecutive data bits having a transition there between by sampling, using an edge sampling point, the transition to produce a sampled transition. The method continues by determining whether the sampled transition is of an intermediate value. The method continues when the sampled transition is not of the intermediate value, by adjusting sampling position of incoming data of the clock and data recovery circuit.