CDR Circuit With Split PI Paths for Stable Low-Power Clock Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock and data recovery (CDR) circuits consume substantial power at high frequencies, experience stability issues due to third-order loop behavior, and require additional components like capacitors and flip-flops, leading to design complexity and data read-out errors.
Innovation Solution
A CDR circuit with separate proportional and integral paths, utilizing a charge pump, integrator circuit, and common-mode feedback amplifier, which includes a capacitor bank and source degenerated switches to reduce power consumption and maintain loop stability, eliminating the need for external capacitors and simplifying design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional CDR circuit includes a charge pump and loop filter circuit (PI controller) to control frequency variations, then jitter in oscillator output is reduced, but power consumption increases substantially at high frequencies
Solution Approach 1:
The loop filter circuit is segmented into separate proportional and integral paths with independent summing nodes. The charge pump current is steered into one of two summing nodes based on phase error detection, allowing independent control of proportional and integral components. This segmentation enables optimized power consumption by activating only necessary paths at different operating conditions.
Solution Approach 2:
The CDR circuit dynamically switches between different operating modes using early-late vote signals. The charge pump dynamically steers current between summing nodes based on phase error conditions, and the circuit adapts its feedback path based on whether early or late sampling is detected, optimizing performance and power consumption dynamically.
2Object-affected harmful factors
If on-chip RC filters are implemented in conventional CDR circuits to filter high frequencies, then frequency filtering is achieved, but design complexity increases due to 3rd order loop behavior
Solution Approach 1:
The complex 3rd order loop filter behavior is extracted and replaced with a simplified architecture using separate proportional and integral paths. The harmful high-frequency components are filtered out through the inherent properties of the integrator circuit and charge pump configuration, eliminating the need for complex on-chip RC filters while reducing design complexity.
Solution Approach 2:
The loop filter characteristics are changed by using an integrator circuit with configurable capacitance values instead of fixed RC time constants. This allows dynamic adjustment of filtering parameters and simplifies the overall design by replacing complex 3rd order behavior with a more manageable structure that achieves similar filtering effects.
3Stability of the object's composition
If conventional CDR circuits require off-chip capacitors to maintain loop stability, then stability is achieved, but design complexity and component count increase
Solution Approach 1:
The off-chip capacitor requirement is eliminated by merging the loop filter functionality directly into the charge pump and integrator circuit. The integrator circuit uses on-chip capacitors that are already present in the differential configuration, combining multiple functions into a single integrated structure that maintains stability without external components.
Solution Approach 2:
The CDR circuit uses its own internal capacitive elements (the integration capacitors in the feedback paths) to provide the necessary stability compensation. The circuit serves itself by utilizing existing components for dual purposes: signal integration and stability maintenance, eliminating the need for separate off-chip capacitors.
4Measurement precision
If conventional CDR circuits use gating and flip flop circuits in the PI controller implementation, then phase detection is achieved, but power consumption increases at high frequencies
Solution Approach 1:
Traditional gating and flip-flop circuits are replaced with a continuous-time charge pump and integrator architecture. The phase detection function is maintained through continuous current steering based on early-late vote signals, substituting discrete switching mechanisms with a continuous analog system that consumes less power at high frequencies while maintaining detection accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution minimizes power consumption at high frequencies, ensures loop stability, and reduces data read-out errors by generating an accurate clock signal with reduced leakage and common-mode frequency variations.
Implementation Method 1
The charge pump receives the first and second ELV signals, and steers a current signal into or out of one of summing nodes based on the first and second ELV signals
Implementation Method 2
The integrator circuit receives the current signal from one of the summing nodes, and generates a first control signal
Implementation Method 3
The CMFB amplifier circuit is connected to the charge pump and a reference voltage source, for receiving the first control signal and a reference voltage signal, respectively, and generates a CMFB control signal
Implementation Method 4
The charge pump further includes first through fourth differential pair of switches such that the first and second differential pair of switches share first and second summing nodes with the third and fourth differential pair of switches, respectively
Data Source
AI summary
A clock and data recovery (CDR) circuit for data sampling includes a sampler, a phase detector, a proportional-integral (PI) controller, and an oscillator. The sampler receives a data signal and a clock signal, and generates first, second, and third sampled signals. The phase detector receives the first, second, and third sampled signals, and generates first and second early-late vote (ELV) signals. The charge pump steers a current signal into or out of one of summing nodes based on the first and second ELV signals. The integrator circuit receives the current signal from one of the summing nodes, and generates a first control signal. The proportional circuit receives the first and second ELV signals, and generates a second control signal. The oscillator receives the first and second control signals from the integrator and proportional circuits, respectively, and generates a clock signal for sampling the data.