CDR Timing Margin Detection Using Delayed Clock Sampling
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits face challenges in timing margin detection due to high circuit complexity and power consumption, particularly when using oversampling or phase interpolators.
Innovation Solution
A timing margin detecting circuit comprising a delay element, controller, sampler, and bit error rate determination circuit, which generates a second clock signal with a controlled delay relative to a second data signal, allowing for determination of timing margin through comparison with a predefined test pattern, thereby reducing circuit complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If timing margin is obtained via oversampling, then timing margin information can be obtained, but clock rate increases and power consumption increases
Solution Approach 1:
The patent applies preliminary action by generating delayed versions of the data signal and clock signal in advance through delay elements before the sampling process. Multiple delayed signals are prepared beforehand, allowing the system to determine timing margin by selecting appropriate delayed signals rather than increasing clock rate for oversampling. This approach obtains timing margin information without the power penalty of higher clock rates.
2Measurement precision
If timing margin is obtained by phase interpolator, then timing margin information can be obtained, but circuit complexity and circuit area increase
Solution Approach 1:
The patent applies segmentation by dividing the timing margin detection function into discrete delay elements that generate multiple delayed signal versions. Instead of using a complex phase interpolator, the system segments the signal path into separate delay stages, each producing a delayed version of the input signals. This segmented approach simplifies the circuit while still providing the necessary phase/timing information for timing margin determination.
Solution Approach 2:
The patent applies copying by creating multiple copies of the data signal and clock signal through the delay elements. Each delay element generates copied versions of the input signals with different delay amounts. These copied signals are then used for sampling and comparison to determine timing margin, replacing the need for complex phase interpolation circuitry.
3Measurement precision
If clock rate is increased for oversampling, then timing margin information can be obtained, but power consumption increases
Solution Approach 1:
The patent applies parameter changes by altering the delay parameter of the delay elements rather than changing the clock rate. Instead of increasing the clock frequency for oversampling, the system varies the delay amount introduced by the delay elements to create different phase relationships between data and clock signals. This parameter change approach obtains timing margin information while maintaining the original clock rate and avoiding increased power consumption.
Data Source
AI summary
A timing margin detecting circuit is provided. The timing margin detecting circuit comprises a delay element, receiving a first data signal and a first clock signal, configured to generate a second data signal and a second clock signal, wherein the second clock signal has a delay relative to the second data signal; a controller, configured to generate the control signal to control the delay of the second clock signal relative to the second data signal; a sampler, coupled to the delay element, configured to generate a sampled data signal according to the second data signal and the second clock signal; and a bit error rate determination circuit, coupled to the sampler, configured to determine whether the sampled data signal is the same as a predefined test pattern and generate a determination result accordingly; wherein the controller determines a timing margin according to the determination result.