CDR False Frequency Lock Detection via Transition Count Comparison
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Solution Overview
Problem
Conventional clock and data recovery (CDR) devices are prone to false locking, especially when recovering multiple information streams at different data rates or a single stream operating at varying rates, and require a pre-programmed reference clock frequency, making them inflexible and difficult to modify.
Innovation Solution
A method and system that detects false clock frequency lock by counting edge transitions in both the raw and recovered data streams, comparing transition counts to determine if the recovered clock is correctly synchronized with the input data stream, allowing for detection of incorrect locking without a priori knowledge of the data stream frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CDR uses pre-programmed reference clock frequency and fixed division ratios, then clock recovery can be achieved for specific frequencies, but the device becomes inflexible and difficult to modify for new or different frequencies
Solution Approach 1:
The patent implements dynamic frequency detection by continuously monitoring edge transitions in the data stream and automatically adjusting the recovered clock frequency to match the actual data rate. This replaces the static, pre-programmed frequency approach with a dynamic system that adapts to varying data rates, resolving the contradiction between reliable clock recovery and frequency adaptability
Solution Approach 2:
The system changes the operational parameters of the PLL by dynamically adjusting the division ratio based on detected edge transition rates. Instead of being fixed to specific frequencies, the division ratio becomes a variable parameter that automatically adapts to different data stream frequencies, enabling both accurate recovery and broad adaptability
2Duration of action of stationary object
If CDR recovers clock from data stream without transitions for extended periods, then clock can be maintained, but the maximum consecutive identical digits specification limits the operational window
Solution Approach 1:
The patent implements a self-adjusting mechanism where the frequency detector continuously monitors edge transitions and automatically adjusts the PLL parameters to maintain optimal locking. This self-service approach ensures the system can adapt to extended periods without transitions by dynamically adjusting to the actual data rate, maintaining both duration and reliability
3Measurement precision
If frequency counters are used to compare refclk and recovered clock frequencies, then false locking can be detected, but the system requires precise pre-programming and is prone to false locking when data rates vary
Solution Approach 1:
The patent extracts the frequency detection function from the traditional reference clock setup by implementing an independent edge transition counter that directly measures the data stream frequency. This separates the frequency measurement function from the pre-programmed reference clock, eliminating the need for complex setup while maintaining precise frequency comparison capability
Solution Approach 2:
The system introduces an intermediary frequency detection mechanism that mediates between the raw data stream and the PLL. This intermediary continuously measures the actual data rate and provides real-time feedback to adjust the recovered clock, replacing the static frequency counter comparison with a dynamic adaptation layer that reduces both complexity and false locking
Data Source
AI summary
A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate—to detect if the clock signal is incorrectly locked to the first rate.