Reference-Less CDR Voltage Control for Jittered USB Type-C Data
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Solution Overview
Problem
Conventional phase locked loop (PLL) or delay locked loop (DLL)-based clock and data recovery circuits struggle with jitter, frequency drift, and ground shifting in USB Type-C communication, making it difficult to recover the clock signal and retime data effectively, especially in noisy environments.
Innovation Solution
A method involving dynamic reference voltage control, where a power mode is determined and reference voltage levels are set based on the power mode, allowing for comparison with incoming data to recover the clock signal and sample data, using a comparator and time-to-digital converters to generate a recovery clock signal, and a digitally controlled oscillator to provide a system clock signal with a higher frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional PLL or DLL-based CDR circuit is used, then clock and data recovery can be performed, but the circuit cannot work properly without a reference clock and is affected by jitter, frequency drift, and ground shifting
Solution Approach 1:
The patent extracts the reference clock requirement from the conventional PLL/DLL-based CDR circuit by implementing a reference-less CDR architecture. The receiver recovers the clock signal directly from the incoming data stream without needing an external reference clock, thereby eliminating the dependency on reference clock availability while maintaining clock and data recovery capability.
Solution Approach 2:
The patent implements dynamic voltage scaling and adaptive hysteresis control in the comparator circuit. The reference voltage and hysteresis voltage are dynamically adjusted based on the detected signal conditions and power mode, enabling the circuit to adapt to varying signal quality, jitter, and ground shifting conditions while maintaining reliable operation.
2Reliability
If a conventional CDR circuit is used, then data can be recovered, but the circuit does not have fast phase track capability and is affected by fast events such as cycle-to-cycle jitter
Solution Approach 1:
The patent implements dynamic hysteresis control where the hysteresis voltage is adjusted in real-time based on the detected signal transitions and power mode. During fast events like cycle-to-cycle jitter, the hysteresis voltage is reduced to enable faster phase tracking. The comparator dynamically adapts its switching characteristics to track rapid phase changes while maintaining stability during normal operation.
Solution Approach 2:
The patent changes the operational parameters of the comparator including reference voltage level and hysteresis voltage based on detected signal conditions and power mode. These parameter changes enable the circuit to respond differently to various signal conditions, achieving fast phase tracking during jitter events while maintaining reliable data recovery under normal conditions.
3Use of energy by moving object
If dynamic reference voltage control is implemented, then power consumption and area are reduced, but the circuit complexity increases
Solution Approach 1:
The patent implements dynamic voltage scaling by changing the reference voltage level based on the detected power mode and signal conditions. The controller adjusts the reference voltage to optimal levels for different operating conditions, reducing power consumption during low-activity modes while maintaining signal integrity during high-activity modes. This parameter adjustment approach achieves power savings without requiring completely separate circuit paths.
Solution Approach 2:
The patent implements a multi-functional controller that performs multiple tasks: detecting power mode, controlling reference voltage level, adjusting hysteresis voltage, and managing comparator operation. This single controller unit handles diverse functions that would otherwise require separate circuits, thereby reducing overall device complexity while achieving dynamic power management and signal conditioning.
Data Source
AI summary
In one aspect, a method includes: determining a power mode of a device; setting a first reference voltage level and a second reference voltage level based at least in part on the power mode; and using at least one of the first reference voltage level and the second reference voltage level for comparison against incoming data.