CDR Voter Tie Handling for Large Frequency Offsets
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Solution Overview
Problem
Existing Clock and Data Recovery (CDR) methods are deficient in handling tie votes, particularly in the presence of large frequency offsets, leading to potential loss of frequency lock, delayed locking time, and increased Bit Error Rate (BER) due to insufficient edge transitions or consecutive identical digits.
Innovation Solution
The proposed solution involves saving recent transition information and applying it during tie votes, using a voter with up and down votes to generate phase adjustment signals, and a multiplexer to select between phase adjustment signals and shift register outputs based on tie signals, ensuring continuous phase alignment and reducing BER.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing CDR voting methods are used to filter noise in edge measurements, then the circuit complexity is reduced, but the reliability deteriorates due to inability to handle tie votes in presence of large frequency offsets
Solution Approach 1:
The patent applies preliminary action by storing the most recent transition information in a shift register before tie votes occur. This stored information is then applied during tie vote periods to maintain frequency tracking, preventing loss of frequency lock without adding complex real-time processing circuits.
2Device complexity
If existing CDR voting methods are used, then the device complexity is kept low, but the locking time increases due to delayed response during tie votes
Solution Approach 1:
The shift register stores transition information in advance, so when tie votes occur during frequency transitions, the CDR can immediately apply the stored information rather than waiting for new transitions. This preliminary storage action significantly reduces locking time while keeping the circuit simple.
3Device complexity
If existing CDR voting methods are used, then the circuit design is simplified, but the bit error rate increases due to loss of frequency lock under large frequency offsets
Solution Approach 1:
The shift register acts as an intermediary element that bridges the voter output and the phase interpolator input. During tie votes, it provides stored transition information to maintain the control signal, ensuring continuous frequency lock and low BER without complicating the overall circuit design.
4Device complexity
If existing CDR methods are used, then the implementation is straightforward, but the frequency offset tolerance deteriorates due to inability to handle consecutive identical digits
Solution Approach 1:
By storing transition information in advance in the shift register, the system maintains the ability to respond to frequency changes even when consecutive identical digits cause tie votes. This preliminary storage action enables the system to tolerate larger frequency offsets without increasing implementation complexity.
Data Source
AI summary
An improved clock data recovery circuit is provided which provides lower bit error rates and faster locking times. In an embodiment, the circuit includes a voter having one or more voter inputs. The voter may generate up votes indicative of a recovered clock having a negative phase offset relative to a given voter input, or down votes indicative of the recovered clock having a positive phase offset. The circuit may include a comparator configured to output a phase adjustment signal and a tie signal. The circuit may further include an M-depth shift register and a multiplexer configured to select either the phase adjustment signal or an output from the shift register as a multiplexer output. The circuit may further include a flip-flop that generates a phase adjustment output signal. The shift register may receive the phase adjustment output signal at a data input of the shift register.