Clock Data Recovery Initialization Using Filter and DFE Phase Error Transition
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Solution Overview
Problem
High-speed data communication systems face challenges in initializing adaptive clock and data recovery (CDR) loops due to interdependence, leading to excessively long or failed convergence times, especially during startup situations.
Innovation Solution
The proposed solution involves a system comprising a filter, decision feedback equalizer (DFE), and phase error detector, where the phase error detector conveys phase errors to the clock generator using phase error estimates from both the filter and DFE outputs, with a gradual transition from filter to DFE-based phase error calculations during initialization and steady-state operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DFE-based CDR system uses the Muller-Mueller algorithm with interdependent adaptation loops for both CDR and DFE initialization, then the system can perform equalization to reduce ISI, but the convergence time becomes excessively long or fails to occur during startup
Solution Approach 1:
The patent applies preliminary action by initializing the CDR loop first before the DFE loop. During the initialization phase, the phase error detector uses outputs from the filter (which does not require adaptation) to establish a stable clock timing. Only after the CDR is stabilized does the system transition to using DFE outputs for phase error detection, allowing the DFE coefficients to be properly adapted. This sequential initialization resolves the mutual dependency problem and reduces convergence time.
2Reliability
If the phase error detector uses outputs from both the filter and DFE during initialization, then the system can gradually transition between initialization modes, but the complexity of the phase error detection mechanism increases
Solution Approach 1:
The patent applies dynamics by making the phase error detection mechanism adaptive and configurable. The phase error detector can dynamically switch between using filter outputs and DFE outputs based on the initialization state. During the initialization phase, it prioritizes filter outputs for stability, then gradually transitions to using DFE outputs as the system stabilizes. This dynamic behavior allows the system to maintain reliability while managing complexity through state-dependent operation.
Data Source
AI summary
An apparatus and methods for recovering a clock and a data stream from a source synchronous input data stream are disclosed. The apparatus comprises a filter, a decision feedback equalizer (DFE), a phase error detector, and a clock generator. The input data stream is coupled to the filter and the DFE. The DFE synchronizes the input data stream to a clock generated by the clock generator. A filter output and a DFE output are each coupled to the phase error detector. During an initialization period, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the filter output and during a period of steady-state operation, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the DFE output. The output of the DFE comprises a recovered data stream.