Correlated Double-Sampling Circuit With Fewer Capacitors
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Solution Overview
Problem
Conventional CMOS image sensor analog-to-digital conversion circuits require a large number of capacitors, occupying significant layout area and increasing chip size due to their complex structure.
Innovation Solution
A correlated double-sampling (CDS) circuit using only two capacitors each for sampling and amplifying reset and signal voltages, with a differential amplifier to produce a difference based on the comparison of these amplified values, and a digital-to-analog converter to control reference voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional CDS circuit uses six capacitors for sampling and amplifying reset and signal voltages, then the circuit achieves proper CDS operation and amplification, but the chip area increases substantially
Solution Approach 1:
The patent merges the functions of multiple capacitors into fewer capacitors. Specifically, the first and second capacitors perform both sampling and amplification functions that traditionally required multiple separate capacitors. The first capacitor samples the reset voltage and works with the second capacitor to amplify the difference between reset and signal voltages, eliminating the need for three capacitors per differential amplifier input terminal.
Solution Approach 2:
The capacitors in the patent are designed to perform multiple functions. The first capacitor both samples the reset voltage and participates in the amplification process. The second capacitor similarly samples the signal voltage and contributes to amplification. This multi-functionality reduces the total number of capacitors from six to two while maintaining CDS operation correctness.
2Area of stationary object
If the CDS circuit uses fewer capacitors, then the chip area is reduced, but the circuit complexity must be managed to maintain proper sampling and amplification functions
Solution Approach 1:
The patent employs preliminary action by using switching circuits to pre-charge the first and second capacitors with the reset and signal voltages before the amplification phase. The switching circuitry is configured to connect the capacitors to the appropriate voltage sources at specific times, ensuring that the sampling occurs before the amplification operation. This temporal sequencing simplifies the overall circuit design by using time-multiplexed operations rather than requiring complex simultaneous multi-capacitor arrangements.
Data Source
AI summary
An analog-to-digital converter (ADC) includes first and second circuits, a differential amplifier, a comparator and a digital-to-analog converter (DAC). The first circuit samples a reset voltage, amplifies the sampled reset voltage, and subtracts a first reference voltage from the amplified reset voltage to produce a first difference. The second circuit samples a signal voltage, amplifies the sampled signal voltage, and subtracts a second reference voltage from the amplified signal voltage to produce a second difference. The differential amplifier produces a third difference based a comparison of the first and second differences from the first and second circuits. The comparator compares an output of the differential amplifier with at least one predetermined comparison voltage and outputs a comparison result as a digital value. The DAC is connected to the first and second circuits and the comparator, and controls the first and second reference voltages in response to the digital value.