Correlated Double Sampling Circuit With Lower Input Capacitance
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Solution Overview
Problem
Current semiconductor devices for signal sampling and amplification in integrated circuits face challenges with noise and require specific clock signals, leading to increased input sampling capacitance, which is not optimal for low noise applications like CCD signal amplification.
Innovation Solution
A non-interleaving architecture circuit with operational amplifiers, input and output capacitors, sampling and holding switches, and combined switches that can sample and amplify signals in one clock cycle without the need for specific clock signals, utilizing a correlated double sampler design for low noise CCD signal amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If specific clock signals are used for signal sampling and amplification, then noise reduction is achieved, but input sampling capacitance increases
Solution Approach 1:
The patent combines sampling and amplification operations into a single integrated circuit block that processes signals in one clock cycle, eliminating the need for separate sampling and amplification stages that would require additional capacitance. The operational amplifier directly amplifies the sampled signal without requiring charge redistribution between separate capacitors.
Solution Approach 2:
The circuit is designed to perform multiple functions (sampling, amplification, and offset calibration) within a single operational amplifier structure, reducing the need for dedicated components for each function. The same operational amplifier handles both signal amplification and offset correction, minimizing total capacitance requirements.
2Reliability
If separate sampling and amplification stages are used, then signal processing is thorough, but device complexity increases
Solution Approach 1:
The patent merges the sampling switch, holding capacitor, and operational amplifier into a single integrated stage that completes both sampling and amplification in one clock cycle. This eliminates the need for separate sampling and amplification circuits, reducing overall device complexity while maintaining signal processing quality.
Solution Approach 2:
The circuit performs offset calibration during the sampling phase itself, before the amplification phase begins. By预先 correcting the operational amplifier offset during sampling, the circuit eliminates the need for separate calibration circuits and reduces overall system complexity.
3Measurement precision
If multiple clock cycles are used for sampling and amplification, then signal accuracy is improved, but processing speed decreases
Solution Approach 1:
The patent combines sampling and amplification into a single operational phase that occurs within one clock cycle. The sampling switch closes to capture the input signal, and the operational amplifier simultaneously amplifies the signal, completing both operations before the clock cycle ends. This eliminates the time delay associated with multi-cycle processing while maintaining signal accuracy through proper circuit design.
Data Source
AI summary
A circuit includes an operational amplifier, a plurality of input capacitors, a plurality of output capacitors, a plurality of sampling switches, a plurality of holding switches, a plurality of combined switches. The input capacitors include a first input capacitor and a second input capacitor. The output capacitors include a first output capacitor and a second output capacitor. The sampling switches include a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch. The holding switches include a first holding switch and a second holding switch. The combined switches include a first combined switch and a second combined switch.