CDS Integrating Circuit Feedback to Prevent Output Jumps
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Solution Overview
Problem
Correlated double sampling integrating circuits experience increasing output jumps due to 1/f noise and mismatch voltages as the number of integrations increases, which affects signal accuracy and noise elimination.
Innovation Solution
Incorporating a feedback module with differential amplifiers and switch units to form negative feedback loops that maintain consistent node signals between integrating and resetting stages, preventing output jumps and noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If correlated double sampling technology is used to eliminate 1/f noise and mismatch voltages, then noise elimination capability is improved, but output jumps increase as the number of integrations increases
Solution Approach 1:
The patent introduces a feedback module with differential amplifiers and switch units that form negative feedback loops. The feedback module detects the output voltage of the integrating circuit and feeds it back to adjust the sampling and holding process, thereby compensating for output jumps and maintaining stable integration results over multiple cycles
Solution Approach 2:
The patent implements a sampling and holding module that performs preliminary sampling and holding of the input signal before integration. By pre-storing the sampled signal in holding capacitors and managing parasitic capacitances in advance, the circuit prepares for integration in a controlled manner, reducing the impact of noise and output jumps during the integration process
2Measurement precision
If multiple integrations are performed to improve signal accuracy, then noise elimination is enhanced, but output jumps become greater
Solution Approach 1:
The feedback module continuously monitors the output voltage and provides corrective feedback to maintain stability. The negative feedback loops formed by the differential amplifiers and switch units adjust the integration process in real-time, compensating for output jumps that accumulate with multiple integrations while preserving the noise elimination benefits
Solution Approach 2:
The patent dynamically changes circuit parameters during operation, including switching between different capacitor connections and adjusting feedback gains. The switch units reconfigure the circuit topology based on the integration stage, optimizing the balance between noise elimination and output stability for each integration cycle
Data Source
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AI summary
Embodiments of the present invention provide a correlated double sampling integrating circuit, including: a sampling and holding module, an energy storage unit and a feedback module; where the sampling and holding module is configured to perform sampling and holding for different input signals, the energy storage unit is configured to store charges corresponding to the input signals upon the sampling and holding to generate node signals (for example, node voltages), and the feedback module is configured to form a negative feedback loop with the energy storage unit to control node signals at an integrating stage to be consistent with node signals at a resetting stage and prevent output jump of the correlated double sampling integrating circuit. Therefore, the correlated double sampling integrating circuit eliminates the noise caused by 1/f noise of the operational amplifier and noise caused by mismatch voltage, and prevents or weakens output jump of the correlated double sampling integrating circuit caused by the increase of the count of integrations.