Correlated Double Sampling Circuit Settling Time Reduction
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Solution Overview
Problem
Conventional image sensors employing correlated double sampling (CDS) technologies face challenges in reducing settling time and increasing operating speed due to the complexity of signal processing units and variations in output signal settling times, which can lead to increased size and reduced efficiency.
Innovation Solution
A CDS circuit with a sampling unit and an output reset unit that resets the output signal to a reference voltage during specific intervals, reducing settling time by triggering successive operations without waiting for the output signal to settle, and includes a comparator with bias units and transistors configured to compare ramp and input signals, and an auto-zero switch to remove noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CDS circuit waits for output signal to settle before triggering successive operations, then measurement precision is improved, but productivity deteriorates due to increased settling time
Solution Approach 1:
The output reset unit performs preliminary resetting of the output signal to a reference voltage level during reset intervals before the comparison operations are completed. This preliminary action prepares the output signal in advance, eliminating the need to wait for natural settling and enabling successive operations to be triggered without delay.
Solution Approach 2:
The circuit uses a reference voltage that copies or replicates the expected settled voltage level of the output signal. By resetting the output signal to this reference voltage level in advance, the circuit creates a known good state that eliminates settling time requirements while maintaining the precision equivalent to a settled signal.
2Productivity
If output reset unit resets output signal during reset intervals, then productivity is improved by reducing settling time, but device complexity increases
Solution Approach 1:
The output reset unit is merged with the existing CDS circuit architecture, sharing control signals and timing structures with the sampling unit. The reset switch, reference voltage source, and control logic are integrated into the existing signal path, adding functionality without requiring completely separate circuit blocks.
Solution Approach 2:
The output reset unit serves multiple functions: it resets the output signal to a reference level, prepares the signal for successive operations, and enables operating speed increases. This multi-functionality justifies the added complexity by delivering multiple benefits from a single integrated unit.
3Measurement precision
If comparator waits for signal settling, then measurement precision is maintained, but loss of time increases
Solution Approach 1:
The output signal is reset to the reference voltage level in advance during the reset interval, before the comparison operation begins. This preliminary action ensures the signal is already at the correct level when comparison starts, eliminating the need for the comparator to wait for settling while maintaining comparison accuracy.
Solution Approach 2:
The reference voltage acts as an intermediary that mediates between the unsettled output signal and the comparison operation. By using the reference voltage as the target reset level, the circuit ensures the output signal reaches a known good state that is equivalent to a settled signal, allowing the comparator to operate immediately without waiting.
Data Source
AI summary
An image sensor includes a sampling circuit, which is responsive to ramp and input signals provided by a pixel array. The sampling circuit is configured to perform a correlated double sampling (CDS) operation on a reset component of the input signal and an image component of the input signal. A reset circuit is also provided, which is configured to reset an output signal generated by the sampling circuit to a first level in response to a reset control signal. This reset control signal can be active during at least one of a first reset interval and a second reset interval. The first reset interval precedes a first comparison interval during which a first comparison operation is performed on the ramp signal and the reset component. The second reset interval precedes a second comparison interval during which a second comparison operation is performed on the ramp signal and the image component.