Correlated Double Sampling Circuit Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional CMOS image sensors experience signal attenuation due to parasitic capacitance, which degrades image signal quality and increases noise, particularly as pixel size and pitch decrease, leading to reduced sensitivity and apparent noise in output images.
Innovation Solution
A correlated double sampling (CDS) circuit design that directly applies the output signal of a unit pixel to the comparator's input terminal without intermediate capacitors, using a differential amplifier to compare the signal with a ramp signal, and incorporating an n-type metal oxide semiconductor (NMOS) capacitor connected to ground, thereby minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If intermediate capacitors and switches are used between the unit pixel circuit and comparator, then signal routing and timing control are enabled, but parasitic capacitance is generated causing signal attenuation and noise
Solution Approach 1:
The patent removes the intermediate capacitor C200 and switch S100 from the signal path between the unit pixel circuit and comparator. By extracting these components that cause parasitic capacitance, the signal is transmitted directly to the comparator input terminal, eliminating the source of signal attenuation and noise while maintaining timing control through the correlated double sampling method
Solution Approach 2:
The patent introduces a virtual ground node as an intermediary element that allows the comparator to receive the pixel signal directly without physical intermediate capacitors. The virtual ground provides a reference potential that enables direct coupling while blocking DC components, effectively mediating the signal transmission without adding parasitic capacitance
2Measurement precision
If pixel size and pitch are reduced to increase resolution, then image quality improves, but parasitic capacitance effects are amplified causing greater signal loss and reduced sensitivity
Solution Approach 1:
By removing the intermediate capacitor that introduces parasitic capacitance, the patent eliminates the primary source of signal loss. This extraction is particularly beneficial for small-pixel designs where signal strength is already limited, as it prevents further degradation and maintains signal integrity even when pixels are miniaturized for higher resolution
Solution Approach 2:
The patent changes the capacitance parameter in the signal path from a finite value (intermediate capacitor C200) to effectively zero by using direct coupling. This parameter change reduces the time constant of the signal path and minimizes charge storage effects, thereby improving signal fidelity in high-resolution sensors with smaller pixels
Data Source
AI summary
A correlated double sampling circuit includes a first capacitor and a comparator. The first capacitor may be configured to receive a ramp signal via a first end. The comparator may be configured to receive the ramp signal and an output signal of a unit pixel circuit via a differential amplifier included in the comparator. The comparator may be also be configured to compare the output signal with the ramp signal and may be configured to directly receive the output signal of the unit pixel circuit at a first input terminal of the differential amplifier. A second input terminal of the differential amplifier is connected to a second end of the first capacitor.